Lines Matching refs:r5
32 VFPFMRX r5, FPINST2, ne @ vmrsne
37 stm \vfp_base, {r2-r5} @ Save FPEXC, FPSCR, FPINST, FPINST2
43 ldm \vfp_base, {r2-r5} @ Load FPEXC, FPSCR, FPINST, FPINST2
50 VFPFMXR FPINST2, r5, ne
94 mrs r5, r11_fiq
118 msr r11_fiq, r5
172 msr r11_fiq, r5
205 mrs r5, SPSR_\mode
206 stm r2, {r3, r4, r5}
222 pop {r3, r4, r5} @ r0, r1, r2
223 stm r2, {r3, r4, r5}
254 mrc p15, 0, r5, c3, c0, 0 @ DACR
267 str r5, [vcpu, #CP15_OFFSET(c3_DACR)]
280 mrc p15, 0, r5, c13, c0, 4 @ TID_PRIV
295 str r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
306 mrrc p15, 0, r4, r5, c7 @ PAR
315 strd r4, r5, [r12]
334 ldrd r4, r5, [r12]
340 mcrr p15, 0, r4, r5, c7 @ PAR
350 ldr r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
363 mcr p15, 0, r5, c13, c0, 4 @ TID_PRIV
378 ldr r5, [vcpu, #CP15_OFFSET(c3_DACR)]
391 mcr p15, 0, r5, c3, c0, 0 @ DACR
417 ldr r5, [r2, #GICH_MISR]
425 ARM_BE8(rev r5, r5 )
434 str r5, [r11, #VGIC_V2_CPU_MISR]
449 mov r5, #0
450 str r5, [r2, #GICH_HCR]
526 add r5, vcpu, r4
527 strd r2, r3, [r5]
568 add r5, vcpu, r4
569 ldrd r2, r3, [r5]