Lines Matching refs:r2
20 VFPFMRX r2, FPEXC
22 orr r6, r2, #FPEXC_EN
26 tst r2, #FPEXC_EX @ Check for VFP Subarchitecture
31 tst r2, #FPEXC_FP2V
33 bic r6, r2, #FPEXC_EX @ FPEXC_EX disable
37 stm \vfp_base, {r2-r5} @ Save FPEXC, FPSCR, FPINST, FPINST2
43 ldm \vfp_base, {r2-r5} @ Load FPEXC, FPSCR, FPINST, FPINST2
46 tst r2, #FPEXC_EX @ Check for VFP Subarchitecture
49 tst r2, #FPEXC_FP2V
52 VFPFMXR FPEXC, r2 @ FPEXC (last, in case !EN)
64 mrs r2, SP_\mode
67 push {r2, r3, r4}
76 mrs r2, ELR_hyp
77 push {r2}
81 mrs r2, SP_usr
83 push {r2, r3}
91 mrs r2, r8_fiq
99 push {r2-r9}
103 pop {r2, r3, r4}
104 msr SP_\mode, r2
114 pop {r2-r9}
115 msr r8_fiq, r2
129 pop {r2, r3}
130 msr SP_usr, r2
134 pop {r2}
135 msr ELR_hyp, r2
148 ldm r1, {r2, r3, r4}
149 msr SP_\mode, r2
168 ldm r1, {r2-r9}
169 msr r8_fiq, r2
179 ldr r2, [vcpu, #VCPU_PC]
181 msr ELR_hyp, r2
185 ldr r2, [vcpu, #VCPU_USR_SP]
187 msr SP_usr, r2
202 add r2, vcpu, \offset
206 stm r2, {r3, r4, r5}
219 add r2, vcpu, #VCPU_USR_REG(3)
220 stm r2, {r3-r12}
221 add r2, vcpu, #VCPU_USR_REG(0)
222 pop {r3, r4, r5} @ r0, r1, r2
223 stm r2, {r3, r4, r5}
224 mrs r2, SP_usr
226 str r2, [vcpu, #VCPU_USR_SP]
230 mrs r2, ELR_hyp
232 str r2, [vcpu, #VCPU_PC]
251 mrc p15, 0, r2, c1, c0, 0 @ SCTLR
262 push {r2-r12} @ Push CP15 registers
264 str r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
268 add r2, vcpu, #CP15_OFFSET(c2_TTBR0)
269 strd r6, r7, [r2]
270 add r2, vcpu, #CP15_OFFSET(c2_TTBR1)
271 strd r8, r9, [r2]
277 mrc p15, 0, r2, c13, c0, 1 @ CID
290 push {r2-r12} @ Push CP15 registers
292 str r2, [vcpu, #CP15_OFFSET(c13_CID)]
305 mrc p15, 0, r2, c14, c1, 0 @ CNTKCTL
311 push {r2,r4-r7}
313 str r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
330 pop {r2,r4-r7}
332 ldr r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
339 mcr p15, 0, r2, c14, c1, 0 @ CNTKCTL
345 pop {r2-r12}
347 ldr r2, [vcpu, #CP15_OFFSET(c13_CID)]
360 mcr p15, 0, r2, c13, c0, 1 @ CID
373 pop {r2-r12}
375 ldr r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
388 mcr p15, 0, r2, c1, c0, 0 @ SCTLR
406 ldr r2, [vcpu, #VCPU_KVM]
407 ldr r2, [r2, #KVM_VGIC_VCTRL]
408 cmp r2, #0
415 ldr r3, [r2, #GICH_HCR]
416 ldr r4, [r2, #GICH_VMCR]
417 ldr r5, [r2, #GICH_MISR]
418 ldr r6, [r2, #GICH_EISR0]
419 ldr r7, [r2, #GICH_EISR1]
420 ldr r8, [r2, #GICH_ELRSR0]
421 ldr r9, [r2, #GICH_ELRSR1]
422 ldr r10, [r2, #GICH_APR]
450 str r5, [r2, #GICH_HCR]
453 add r2, r2, #GICH_LR0
456 1: ldr r6, [r2], #4
471 ldr r2, [vcpu, #VCPU_KVM]
472 ldr r2, [r2, #KVM_VGIC_VCTRL]
473 cmp r2, #0
487 str r3, [r2, #GICH_HCR]
488 str r4, [r2, #GICH_VMCR]
489 str r8, [r2, #GICH_APR]
492 add r2, r2, #GICH_LR0
497 str r6, [r2], #4
515 ldr r2, [r4, #KVM_TIMER_ENABLED]
516 cmp r2, #0
519 mrc p15, 0, r2, c14, c3, 1 @ CNTV_CTL
520 str r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
524 mrrc p15, 3, rr_lo_hi(r2, r3), c14 @ CNTV_CVAL
527 strd r2, r3, [r5]
530 mov r2, #0
531 mcrr p15, 4, r2, r2, c14 @ CNTVOFF
534 mov r2, #0 @ Clear ENABLE
535 mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
538 mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL
539 orr r2, r2, #(CNTHCTL_PL1PCEN | CNTHCTL_PL1PCTEN)
540 mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL
553 mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL
554 orr r2, r2, #CNTHCTL_PL1PCTEN
555 bic r2, r2, #CNTHCTL_PL1PCEN
556 mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL
559 ldr r2, [r4, #KVM_TIMER_ENABLED]
560 cmp r2, #0
563 ldr r2, [r4, #KVM_TIMER_CNTVOFF]
565 mcrr p15, 4, rr_lo_hi(r2, r3), c14 @ CNTVOFF
569 ldrd r2, r3, [r5]
570 mcrr p15, 3, rr_lo_hi(r2, r3), c14 @ CNTV_CVAL
573 ldr r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
574 and r2, r2, #3
575 mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
585 mrc p15, 4, r2, c1, c1, 3
588 orr r2, r2, r3 @ Trap CR{15}
590 bic r2, r2, r3 @ Don't trap any CRx accesses
613 tst r2, #(HCPTR_TCP(10) | HCPTR_TCP(11))
627 mrc p15, 4, r2, c1, c1, 1
630 orr r2, r2, r3 @ Trap some perfmon accesses
632 bic r2, r2, r3 @ Don't trap any perfmon accesses