Lines Matching refs:r11
258 mrc p15, 0, r11, c10, c2, 1 @ NMRR
273 str r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
286 mrc p15, 0, r11, c6, c0, 2 @ IFAR
301 str r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
356 ldr r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
369 mcr p15, 0, r11, c6, c0, 2 @ IFAR
384 ldr r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
395 mcr p15, 0, r11, c10, c2, 1 @ NMRR
412 add r11, vcpu, #VCPU_VGIC_CPU
432 str r3, [r11, #VGIC_V2_CPU_HCR]
433 str r4, [r11, #VGIC_V2_CPU_VMCR]
434 str r5, [r11, #VGIC_V2_CPU_MISR]
436 str r6, [r11, #(VGIC_V2_CPU_EISR + 4)]
437 str r7, [r11, #VGIC_V2_CPU_EISR]
438 str r8, [r11, #(VGIC_V2_CPU_ELRSR + 4)]
439 str r9, [r11, #VGIC_V2_CPU_ELRSR]
441 str r6, [r11, #VGIC_V2_CPU_EISR]
442 str r7, [r11, #(VGIC_V2_CPU_EISR + 4)]
443 str r8, [r11, #VGIC_V2_CPU_ELRSR]
444 str r9, [r11, #(VGIC_V2_CPU_ELRSR + 4)]
446 str r10, [r11, #VGIC_V2_CPU_APR]
454 add r3, r11, #VGIC_V2_CPU_LR
455 ldr r4, [r11, #VGIC_CPU_NR_LR]
477 add r11, vcpu, #VCPU_VGIC_CPU
480 ldr r3, [r11, #VGIC_V2_CPU_HCR]
481 ldr r4, [r11, #VGIC_V2_CPU_VMCR]
482 ldr r8, [r11, #VGIC_V2_CPU_APR]
493 add r3, r11, #VGIC_V2_CPU_LR
494 ldr r4, [r11, #VGIC_CPU_NR_LR]