39 #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
50 #define IOP3XX_ATUCCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0109)
55 #define IOP3XX_IABAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0110)
56 #define IOP3XX_IAUBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0114)
57 #define IOP3XX_IABAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0118)
58 #define IOP3XX_IAUBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x011c)
59 #define IOP3XX_IABAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0120)
60 #define IOP3XX_IAUBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0124)
63 #define IOP3XX_ERBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0130)
68 #define IOP3XX_IALR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0140)
69 #define IOP3XX_IATVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0144)
70 #define IOP3XX_ERLR		(volatile u32 *)IOP3XX_REG_ADDR(0x0148)
71 #define IOP3XX_ERTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x014c)
72 #define IOP3XX_IALR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0150)
73 #define IOP3XX_IALR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0154)
74 #define IOP3XX_IATVR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0158)
75 #define IOP3XX_OIOWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x015c)
76 #define IOP3XX_OMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0160)
77 #define IOP3XX_OUMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0164)
78 #define IOP3XX_OMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0168)
79 #define IOP3XX_OUMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x016c)
80 #define IOP3XX_OUDWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x0178)
81 #define IOP3XX_ATUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0180)
82 #define IOP3XX_PCSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0184)
83 #define IOP3XX_ATUISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0188)
84 #define IOP3XX_ATUIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x018c)
85 #define IOP3XX_IABAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0190)
86 #define IOP3XX_IAUBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0194)
87 #define IOP3XX_IALR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0198)
88 #define IOP3XX_IATVR3		(volatile u32 *)IOP3XX_REG_ADDR(0x019c)
89 #define IOP3XX_OCCAR		(volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
90 #define IOP3XX_OCCDR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
91 #define IOP3XX_PDSCR		(volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
99 #define IOP3XX_PCIXSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
100 #define IOP3XX_PCIIRSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
110 #define IOP3XX_IMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0310)
111 #define IOP3XX_IMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0314)
112 #define IOP3XX_OMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0318)
113 #define IOP3XX_OMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x031c)
114 #define IOP3XX_IDR		(volatile u32 *)IOP3XX_REG_ADDR(0x0320)
115 #define IOP3XX_IISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0324)
116 #define IOP3XX_IIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0328)
117 #define IOP3XX_ODR		(volatile u32 *)IOP3XX_REG_ADDR(0x032c)
118 #define IOP3XX_OISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0330)
119 #define IOP3XX_OIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0334)
120 #define IOP3XX_MUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0350)
121 #define IOP3XX_QBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0354)
122 #define IOP3XX_IFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0360)
123 #define IOP3XX_IFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0364)
124 #define IOP3XX_IPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0368)
125 #define IOP3XX_IPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x036c)
126 #define IOP3XX_OFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0370)
127 #define IOP3XX_OFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0374)
128 #define IOP3XX_OPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0378)
129 #define IOP3XX_OPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x037c)
130 #define IOP3XX_IAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0380)
138 #define IOP3XX_PBCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0680)
139 #define IOP3XX_PBISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0684)
140 #define IOP3XX_PBBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0688)
141 #define IOP3XX_PBLR0		(volatile u32 *)IOP3XX_REG_ADDR(0x068c)
142 #define IOP3XX_PBBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0690)
143 #define IOP3XX_PBLR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0694)
144 #define IOP3XX_PBBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0698)
145 #define IOP3XX_PBLR2		(volatile u32 *)IOP3XX_REG_ADDR(0x069c)
146 #define IOP3XX_PBBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
147 #define IOP3XX_PBLR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
148 #define IOP3XX_PBBAR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
149 #define IOP3XX_PBLR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
150 #define IOP3XX_PBBAR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
151 #define IOP3XX_PBLR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
152 #define IOP3XX_PMBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
153 #define IOP3XX_PMBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
154 #define IOP3XX_PMBR2		(volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
157 #define IOP3XX_GTMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0700)
158 #define IOP3XX_ESR		(volatile u32 *)IOP3XX_REG_ADDR(0x0704)
159 #define IOP3XX_EMISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0708)
160 #define IOP3XX_GTSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)
162 #define IOP3XX_PERCR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)
165 #define IOP3XX_TU_TMR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0000)
166 #define IOP3XX_TU_TMR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0004)
167 #define IOP3XX_TU_TCR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0008)
168 #define IOP3XX_TU_TCR1		(volatile u32 *)IOP3XX_TIMER_REG(0x000c)
169 #define IOP3XX_TU_TRR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0010)
170 #define IOP3XX_TU_TRR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0014)
171 #define IOP3XX_TU_TISR		(volatile u32 *)IOP3XX_TIMER_REG(0x0018)
172 #define IOP3XX_TU_WDTCR		(volatile u32 *)IOP3XX_TIMER_REG(0x001c)
190 #define IOP3XX_ICR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1680)
191 #define IOP3XX_ISR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1684)
192 #define IOP3XX_ISAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1688)
193 #define IOP3XX_IDBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x168c)
194 #define IOP3XX_IBMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1694)
195 #define IOP3XX_ICR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
196 #define IOP3XX_ISR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
197 #define IOP3XX_ISAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
198 #define IOP3XX_IDBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
199 #define IOP3XX_IBMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
221 static inline u32 read_tmr0(void)  in read_tmr0()
223 	u32 val;  in read_tmr0()
228 static inline void write_tmr0(u32 val)  in write_tmr0()
233 static inline void write_tmr1(u32 val)  in write_tmr1()
238 static inline u32 read_tcr0(void)  in read_tcr0()
240 	u32 val;  in read_tcr0()
245 static inline void write_tcr0(u32 val)  in write_tcr0()
250 static inline u32 read_tcr1(void)  in read_tcr1()
252 	u32 val;  in read_tcr1()
257 static inline void write_tcr1(u32 val)  in write_tcr1()
262 static inline void write_trr0(u32 val)  in write_trr0()
267 static inline void write_trr1(u32 val)  in write_trr1()
272 static inline void write_tisr(u32 val)  in write_tisr()
277 static inline u32 read_wdtcr(void)  in read_wdtcr()
279 	u32 val;  in read_wdtcr()
283 static inline void write_wdtcr(u32 val)  in write_wdtcr()
294 static inline u32 read_rcsr(void)  in read_rcsr()
298 static inline void write_wdtsr(u32 val)  in write_wdtsr()