84 #define rounds2_0_63(ra, rb, rc, rd, re, rf, rg, rh, rw0, rw1, rw01q, rw2, \  argument
100 	vbsl.64 RT7, rf, rg; \
137 	vadd.u64 RT1, RT1, rg; \
153 	veor.64 rg, RT2, RT3; \
164 	vadd.u64 rg, rg, RT0; \
166 	vadd.u64 rg, rg, RT1; /* g+=t1; */ \
195 #define rounds2_64_79(ra, rb, rc, rd, re, rf, rg, rh, rw0, rw1, \  argument
212 	vbsl.64 RT7, rf, rg; \
249 	vadd.u64 RT1, RT1, rg; \
265 	veor.64 rg, RT2, RT3;
266 #define vadd_rg_RT0(rg) \  argument
267 	vadd.u64 rg, rg, RT0;
268 #define vadd_rg_RT1(rg) \  argument
269 	vadd.u64 rg, rg, RT1; /* g+=t1; */