168 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,  in edma_or_array2()  argument
171 	edma_or(ctlr, offset + ((i*2 + j) << 2), or);  in edma_or_array2()
173 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,  in edma_write_array2()  argument
176 	edma_write(ctlr, offset + ((i*2 + j) << 2), val);  in edma_write_array2()
443 		int j = -1;  in dma_ccerr_handler()  local
445 			j = 0;  in dma_ccerr_handler()
447 			j = 1;  in dma_ccerr_handler()
448 		if (j >= 0) {  in dma_ccerr_handler()
449 			dev_dbg(data, "EMR%d %08x\n", j,  in dma_ccerr_handler()
450 					edma_read_array(ctlr, EDMA_EMR, j));  in dma_ccerr_handler()
452 				int k = (j << 5) + i;  in dma_ccerr_handler()
453 				if (edma_read_array(ctlr, EDMA_EMR, j) &  in dma_ccerr_handler()
456 					edma_write_array(ctlr, EDMA_EMCR, j,  in dma_ccerr_handler()
460 								j, BIT(i));  in dma_ccerr_handler()
517 	int i, j;  in reserve_contiguous_slots()  local
523 		j = EDMA_CHAN_SLOT(i);  in reserve_contiguous_slots()
524 		if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {  in reserve_contiguous_slots()
530 			set_bit(j, tmp_inuse);  in reserve_contiguous_slots()
535 			clear_bit(j, tmp_inuse);  in reserve_contiguous_slots()
555 	j = start_slot;  in reserve_contiguous_slots()
556 	for_each_set_bit_from(j, tmp_inuse, stop_slot)  in reserve_contiguous_slots()
557 		clear_bit(j, edma_cc[ctlr]->edma_inuse);  in reserve_contiguous_slots()
562 	for (j = i - num_slots + 1; j <= i; ++j)  in reserve_contiguous_slots()
563 		memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),  in reserve_contiguous_slots()
1301 		int j = channel >> 5;  in edma_start()  local
1306 			pr_debug("EDMA: ESR%d %08x\n", j,  in edma_start()
1307 				edma_shadow0_read_array(ctlr, SH_ESR, j));  in edma_start()
1308 			edma_shadow0_write_array(ctlr, SH_ESR, j, mask);  in edma_start()
1313 		pr_debug("EDMA: ER%d %08x\n", j,  in edma_start()
1314 			edma_shadow0_read_array(ctlr, SH_ER, j));  in edma_start()
1316 		edma_write_array(ctlr, EDMA_ECR, j, mask);  in edma_start()
1317 		edma_write_array(ctlr, EDMA_EMCR, j, mask);  in edma_start()
1319 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);  in edma_start()
1320 		edma_shadow0_write_array(ctlr, SH_EESR, j, mask);  in edma_start()
1321 		pr_debug("EDMA: EER%d %08x\n", j,  in edma_start()
1322 			edma_shadow0_read_array(ctlr, SH_EER, j));  in edma_start()
1347 		int j = channel >> 5;  in edma_stop()  local
1350 		edma_shadow0_write_array(ctlr, SH_EECR, j, mask);  in edma_stop()
1351 		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);  in edma_stop()
1352 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);  in edma_stop()
1353 		edma_write_array(ctlr, EDMA_EMCR, j, mask);  in edma_stop()
1355 		pr_debug("EDMA: EER%d %08x\n", j,  in edma_stop()
1356 				edma_shadow0_read_array(ctlr, SH_EER, j));  in edma_stop()
1386 		int j = (channel >> 5);  in edma_clean_channel()  local
1389 		pr_debug("EDMA: EMR%d %08x\n", j,  in edma_clean_channel()
1390 				edma_read_array(ctlr, EDMA_EMR, j));  in edma_clean_channel()
1391 		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);  in edma_clean_channel()
1393 		edma_write_array(ctlr, EDMA_EMCR, j, mask);  in edma_clean_channel()
1395 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);  in edma_clean_channel()
1618 	int			i, j, off, ln, found = 0;  in edma_probe()  local
1663 	for (j = 0; j < EDMA_MAX_CC; j++) {  in edma_probe()
1664 		if (!info[j]) {  in edma_probe()
1670 			ret = of_address_to_resource(node, j, &res[j]);  in edma_probe()
1672 				r[j] = &res[j];  in edma_probe()
1674 			sprintf(res_name, "edma_cc%d", j);  in edma_probe()
1675 			r[j] = platform_get_resource_byname(pdev,  in edma_probe()
1679 		if (!r[j]) {  in edma_probe()
1688 		edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);  in edma_probe()
1689 		if (IS_ERR(edmacc_regs_base[j]))  in edma_probe()
1690 			return PTR_ERR(edmacc_regs_base[j]);  in edma_probe()
1692 		edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),  in edma_probe()
1694 		if (!edma_cc[j])  in edma_probe()
1698 		ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);  in edma_probe()
1702 		edma_cc[j]->default_queue = info[j]->default_queue;  in edma_probe()
1705 			edmacc_regs_base[j]);  in edma_probe()
1707 		for (i = 0; i < edma_cc[j]->num_slots; i++)  in edma_probe()
1708 			memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),  in edma_probe()
1712 		memset(edma_cc[j]->edma_unused, 0xff,  in edma_probe()
1713 			sizeof(edma_cc[j]->edma_unused));  in edma_probe()
1715 		if (info[j]->rsv) {  in edma_probe()
1718 			rsv_chans = info[j]->rsv->rsv_chans;  in edma_probe()
1724 						  edma_cc[j]->edma_unused);  in edma_probe()
1729 			rsv_slots = info[j]->rsv->rsv_slots;  in edma_probe()
1735 						edma_cc[j]->edma_inuse);  in edma_probe()
1741 		xbar_chans = info[j]->xbar_chans;  in edma_probe()
1746 					   edma_cc[j]->edma_unused);  in edma_probe()
1751 			irq[j] = irq_of_parse_and_map(node, 0);  in edma_probe()
1752 			err_irq[j] = irq_of_parse_and_map(node, 2);  in edma_probe()
1756 			sprintf(irq_name, "edma%d", j);  in edma_probe()
1757 			irq[j] = platform_get_irq_byname(pdev, irq_name);  in edma_probe()
1759 			sprintf(irq_name, "edma%d_err", j);  in edma_probe()
1760 			err_irq[j] = platform_get_irq_byname(pdev, irq_name);  in edma_probe()
1762 		edma_cc[j]->irq_res_start = irq[j];  in edma_probe()
1763 		edma_cc[j]->irq_res_end = err_irq[j];  in edma_probe()
1765 		status = devm_request_irq(dev, irq[j], dma_irq_handler, 0,  in edma_probe()
1770 				irq[j], status);  in edma_probe()
1774 		status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0,  in edma_probe()
1779 				err_irq[j], status);  in edma_probe()
1783 		for (i = 0; i < edma_cc[j]->num_channels; i++)  in edma_probe()
1784 			map_dmach_queue(j, i, info[j]->default_queue);  in edma_probe()
1786 		queue_priority_mapping = info[j]->queue_priority_mapping;  in edma_probe()
1790 			assign_priority_to_queue(j,  in edma_probe()
1797 		if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)  in edma_probe()
1798 			map_dmach_param(j);  in edma_probe()
1800 		for (i = 0; i < edma_cc[j]->num_region; i++) {  in edma_probe()
1801 			edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);  in edma_probe()
1802 			edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);  in edma_probe()
1803 			edma_write_array(j, EDMA_QRAE, i, 0x0);  in edma_probe()
1805 		edma_cc[j]->info = info[j];  in edma_probe()
1808 		edma_dev_info.id = j;  in edma_probe()
1818 	int i, j;  in edma_pm_resume()  local
1820 	for (j = 0; j < arch_num_cc; j++) {  in edma_pm_resume()
1821 		struct edma *cc = edma_cc[j];  in edma_pm_resume()
1829 			assign_priority_to_queue(j,  in edma_pm_resume()
1837 		if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)  in edma_pm_resume()
1838 			map_dmach_param(j);  in edma_pm_resume()
1843 				edma_or_array2(j, EDMA_DRAE, 0, i >> 5,  in edma_pm_resume()