Lines Matching refs:edma_shadow0_write_array
191 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, in edma_shadow0_write_array() function
338 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, in setup_dma_interrupt()
345 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, in setup_dma_interrupt()
347 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, in setup_dma_interrupt()
405 edma_shadow0_write_array(ctlr, SH_ICR, bank, in dma_irq_handler()
459 edma_shadow0_write_array(ctlr, SH_SECR, in dma_ccerr_handler()
1239 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); in edma_pause()
1260 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); in edma_resume()
1274 edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask); in edma_trigger_channel()
1308 edma_shadow0_write_array(ctlr, SH_ESR, j, mask); in edma_start()
1319 edma_shadow0_write_array(ctlr, SH_SECR, j, mask); in edma_start()
1320 edma_shadow0_write_array(ctlr, SH_EESR, j, mask); in edma_start()
1350 edma_shadow0_write_array(ctlr, SH_EECR, j, mask); in edma_stop()
1351 edma_shadow0_write_array(ctlr, SH_ECR, j, mask); in edma_stop()
1352 edma_shadow0_write_array(ctlr, SH_SECR, j, mask); in edma_stop()
1391 edma_shadow0_write_array(ctlr, SH_ECR, j, mask); in edma_clean_channel()
1395 edma_shadow0_write_array(ctlr, SH_SECR, j, mask); in edma_clean_channel()