Lines Matching refs:ctlr
121 static inline unsigned int edma_read(unsigned ctlr, int offset) in edma_read() argument
123 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); in edma_read()
126 static inline void edma_write(unsigned ctlr, int offset, int val) in edma_write() argument
128 __raw_writel(val, edmacc_regs_base[ctlr] + offset); in edma_write()
130 static inline void edma_modify(unsigned ctlr, int offset, unsigned and, in edma_modify() argument
133 unsigned val = edma_read(ctlr, offset); in edma_modify()
136 edma_write(ctlr, offset, val); in edma_modify()
138 static inline void edma_and(unsigned ctlr, int offset, unsigned and) in edma_and() argument
140 unsigned val = edma_read(ctlr, offset); in edma_and()
142 edma_write(ctlr, offset, val); in edma_and()
144 static inline void edma_or(unsigned ctlr, int offset, unsigned or) in edma_or() argument
146 unsigned val = edma_read(ctlr, offset); in edma_or()
148 edma_write(ctlr, offset, val); in edma_or()
150 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) in edma_read_array() argument
152 return edma_read(ctlr, offset + (i << 2)); in edma_read_array()
154 static inline void edma_write_array(unsigned ctlr, int offset, int i, in edma_write_array() argument
157 edma_write(ctlr, offset + (i << 2), val); in edma_write_array()
159 static inline void edma_modify_array(unsigned ctlr, int offset, int i, in edma_modify_array() argument
162 edma_modify(ctlr, offset + (i << 2), and, or); in edma_modify_array()
164 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) in edma_or_array() argument
166 edma_or(ctlr, offset + (i << 2), or); in edma_or_array()
168 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, in edma_or_array2() argument
171 edma_or(ctlr, offset + ((i*2 + j) << 2), or); in edma_or_array2()
173 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, in edma_write_array2() argument
176 edma_write(ctlr, offset + ((i*2 + j) << 2), val); in edma_write_array2()
178 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) in edma_shadow0_read() argument
180 return edma_read(ctlr, EDMA_SHADOW0 + offset); in edma_shadow0_read()
182 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, in edma_shadow0_read_array() argument
185 return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); in edma_shadow0_read_array()
187 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) in edma_shadow0_write() argument
189 edma_write(ctlr, EDMA_SHADOW0 + offset, val); in edma_shadow0_write()
191 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, in edma_shadow0_write_array() argument
194 edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); in edma_shadow0_write_array()
196 static inline unsigned int edma_parm_read(unsigned ctlr, int offset, in edma_parm_read() argument
199 return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); in edma_parm_read()
201 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, in edma_parm_write() argument
204 edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); in edma_parm_write()
206 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, in edma_parm_modify() argument
209 edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); in edma_parm_modify()
211 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, in edma_parm_and() argument
214 edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); in edma_parm_and()
216 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, in edma_parm_or() argument
219 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); in edma_parm_or()
287 static void map_dmach_queue(unsigned ctlr, unsigned ch_no, in map_dmach_queue() argument
294 queue_no = edma_cc[ctlr]->default_queue; in map_dmach_queue()
297 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), in map_dmach_queue()
301 static void assign_priority_to_queue(unsigned ctlr, int queue_no, in assign_priority_to_queue() argument
305 edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), in assign_priority_to_queue()
320 static void map_dmach_param(unsigned ctlr) in map_dmach_param() argument
324 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); in map_dmach_param()
332 unsigned ctlr; in setup_dma_interrupt() local
334 ctlr = EDMA_CTLR(lch); in setup_dma_interrupt()
338 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, in setup_dma_interrupt()
341 edma_cc[ctlr]->intr_data[lch].callback = callback; in setup_dma_interrupt()
342 edma_cc[ctlr]->intr_data[lch].data = data; in setup_dma_interrupt()
345 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, in setup_dma_interrupt()
347 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, in setup_dma_interrupt()
370 int ctlr; in dma_irq_handler() local
375 ctlr = irq2ctlr(irq); in dma_irq_handler()
376 if (ctlr < 0) in dma_irq_handler()
381 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0); in dma_irq_handler()
383 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1); in dma_irq_handler()
386 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1); in dma_irq_handler()
389 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0); in dma_irq_handler()
405 edma_shadow0_write_array(ctlr, SH_ICR, bank, in dma_irq_handler()
407 if (edma_cc[ctlr]->intr_data[channel].callback) in dma_irq_handler()
408 edma_cc[ctlr]->intr_data[channel].callback( in dma_irq_handler()
409 EDMA_CTLR_CHAN(ctlr, channel), in dma_irq_handler()
411 edma_cc[ctlr]->intr_data[channel].data); in dma_irq_handler()
415 edma_shadow0_write(ctlr, SH_IEVAL, 1); in dma_irq_handler()
427 int ctlr; in dma_ccerr_handler() local
430 ctlr = irq2ctlr(irq); in dma_ccerr_handler()
431 if (ctlr < 0) in dma_ccerr_handler()
436 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && in dma_ccerr_handler()
437 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && in dma_ccerr_handler()
438 (edma_read(ctlr, EDMA_QEMR) == 0) && in dma_ccerr_handler()
439 (edma_read(ctlr, EDMA_CCERR) == 0)) in dma_ccerr_handler()
444 if (edma_read_array(ctlr, EDMA_EMR, 0)) in dma_ccerr_handler()
446 else if (edma_read_array(ctlr, EDMA_EMR, 1)) in dma_ccerr_handler()
450 edma_read_array(ctlr, EDMA_EMR, j)); in dma_ccerr_handler()
453 if (edma_read_array(ctlr, EDMA_EMR, j) & in dma_ccerr_handler()
456 edma_write_array(ctlr, EDMA_EMCR, j, in dma_ccerr_handler()
459 edma_shadow0_write_array(ctlr, SH_SECR, in dma_ccerr_handler()
461 if (edma_cc[ctlr]->intr_data[k]. in dma_ccerr_handler()
463 edma_cc[ctlr]->intr_data[k]. in dma_ccerr_handler()
465 EDMA_CTLR_CHAN(ctlr, k), in dma_ccerr_handler()
467 edma_cc[ctlr]->intr_data in dma_ccerr_handler()
472 } else if (edma_read(ctlr, EDMA_QEMR)) { in dma_ccerr_handler()
474 edma_read(ctlr, EDMA_QEMR)); in dma_ccerr_handler()
476 if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { in dma_ccerr_handler()
478 edma_write(ctlr, EDMA_QEMCR, BIT(i)); in dma_ccerr_handler()
479 edma_shadow0_write(ctlr, SH_QSECR, in dma_ccerr_handler()
485 } else if (edma_read(ctlr, EDMA_CCERR)) { in dma_ccerr_handler()
487 edma_read(ctlr, EDMA_CCERR)); in dma_ccerr_handler()
492 if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { in dma_ccerr_handler()
494 edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); in dma_ccerr_handler()
500 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && in dma_ccerr_handler()
501 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && in dma_ccerr_handler()
502 (edma_read(ctlr, EDMA_QEMR) == 0) && in dma_ccerr_handler()
503 (edma_read(ctlr, EDMA_CCERR) == 0)) in dma_ccerr_handler()
509 edma_write(ctlr, EDMA_EEVAL, 1); in dma_ccerr_handler()
513 static int reserve_contiguous_slots(int ctlr, unsigned int id, in reserve_contiguous_slots() argument
522 for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { in reserve_contiguous_slots()
524 if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { in reserve_contiguous_slots()
552 if (i == edma_cc[ctlr]->num_slots) in reserve_contiguous_slots()
557 clear_bit(j, edma_cc[ctlr]->edma_inuse); in reserve_contiguous_slots()
563 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), in reserve_contiguous_slots()
566 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); in reserve_contiguous_slots()
572 int i, count, ctlr; in prepare_unused_channel_list() local
601 ctlr = EDMA_CTLR(pdev->resource[i].start); in prepare_unused_channel_list()
603 edma_cc[ctlr]->edma_unused); in prepare_unused_channel_list()
651 unsigned i, done = 0, ctlr = 0; in edma_alloc_channel() local
669 ctlr = EDMA_CTLR(channel); in edma_alloc_channel()
685 ctlr = i; in edma_alloc_channel()
695 } else if (channel >= edma_cc[ctlr]->num_channels) { in edma_alloc_channel()
697 } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { in edma_alloc_channel()
702 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); in edma_alloc_channel()
705 edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); in edma_alloc_channel()
706 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), in edma_alloc_channel()
710 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), in edma_alloc_channel()
713 map_dmach_queue(ctlr, channel, eventq_no); in edma_alloc_channel()
715 return EDMA_CTLR_CHAN(ctlr, channel); in edma_alloc_channel()
733 unsigned ctlr; in edma_free_channel() local
735 ctlr = EDMA_CTLR(channel); in edma_free_channel()
738 if (channel >= edma_cc[ctlr]->num_channels) in edma_free_channel()
744 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), in edma_free_channel()
746 clear_bit(channel, edma_cc[ctlr]->edma_inuse); in edma_free_channel()
764 int edma_alloc_slot(unsigned ctlr, int slot) in edma_alloc_slot() argument
766 if (!edma_cc[ctlr]) in edma_alloc_slot()
773 slot = edma_cc[ctlr]->num_channels; in edma_alloc_slot()
775 slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, in edma_alloc_slot()
776 edma_cc[ctlr]->num_slots, slot); in edma_alloc_slot()
777 if (slot == edma_cc[ctlr]->num_slots) in edma_alloc_slot()
779 if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) in edma_alloc_slot()
782 } else if (slot < edma_cc[ctlr]->num_channels || in edma_alloc_slot()
783 slot >= edma_cc[ctlr]->num_slots) { in edma_alloc_slot()
785 } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { in edma_alloc_slot()
789 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), in edma_alloc_slot()
792 return EDMA_CTLR_CHAN(ctlr, slot); in edma_alloc_slot()
806 unsigned ctlr; in edma_free_slot() local
808 ctlr = EDMA_CTLR(slot); in edma_free_slot()
811 if (slot < edma_cc[ctlr]->num_channels || in edma_free_slot()
812 slot >= edma_cc[ctlr]->num_slots) in edma_free_slot()
815 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), in edma_free_slot()
817 clear_bit(slot, edma_cc[ctlr]->edma_inuse); in edma_free_slot()
847 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) in edma_alloc_cont_slots() argument
855 (slot < edma_cc[ctlr]->num_channels || in edma_alloc_cont_slots()
856 slot >= edma_cc[ctlr]->num_slots)) in edma_alloc_cont_slots()
865 (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) in edma_alloc_cont_slots()
870 return reserve_contiguous_slots(ctlr, id, count, in edma_alloc_cont_slots()
871 edma_cc[ctlr]->num_channels); in edma_alloc_cont_slots()
874 return reserve_contiguous_slots(ctlr, id, count, slot); in edma_alloc_cont_slots()
897 unsigned ctlr, slot_to_free; in edma_free_cont_slots() local
900 ctlr = EDMA_CTLR(slot); in edma_free_cont_slots()
903 if (slot < edma_cc[ctlr]->num_channels || in edma_free_cont_slots()
904 slot >= edma_cc[ctlr]->num_slots || in edma_free_cont_slots()
909 ctlr = EDMA_CTLR(i); in edma_free_cont_slots()
912 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), in edma_free_cont_slots()
914 clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); in edma_free_cont_slots()
939 unsigned ctlr; in edma_set_src() local
941 ctlr = EDMA_CTLR(slot); in edma_set_src()
944 if (slot < edma_cc[ctlr]->num_slots) { in edma_set_src()
945 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); in edma_set_src()
954 edma_parm_write(ctlr, PARM_OPT, slot, i); in edma_set_src()
958 edma_parm_write(ctlr, PARM_SRC, slot, src_port); in edma_set_src()
977 unsigned ctlr; in edma_set_dest() local
979 ctlr = EDMA_CTLR(slot); in edma_set_dest()
982 if (slot < edma_cc[ctlr]->num_slots) { in edma_set_dest()
983 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); in edma_set_dest()
992 edma_parm_write(ctlr, PARM_OPT, slot, i); in edma_set_dest()
995 edma_parm_write(ctlr, PARM_DST, slot, dest_port); in edma_set_dest()
1009 u32 offs, ctlr = EDMA_CTLR(slot); in edma_get_position() local
1016 return edma_read(ctlr, offs); in edma_get_position()
1031 unsigned ctlr; in edma_set_src_index() local
1033 ctlr = EDMA_CTLR(slot); in edma_set_src_index()
1036 if (slot < edma_cc[ctlr]->num_slots) { in edma_set_src_index()
1037 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, in edma_set_src_index()
1039 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, in edma_set_src_index()
1057 unsigned ctlr; in edma_set_dest_index() local
1059 ctlr = EDMA_CTLR(slot); in edma_set_dest_index()
1062 if (slot < edma_cc[ctlr]->num_slots) { in edma_set_dest_index()
1063 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, in edma_set_dest_index()
1065 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, in edma_set_dest_index()
1104 unsigned ctlr; in edma_set_transfer_params() local
1106 ctlr = EDMA_CTLR(slot); in edma_set_transfer_params()
1109 if (slot < edma_cc[ctlr]->num_slots) { in edma_set_transfer_params()
1110 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, in edma_set_transfer_params()
1113 edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); in edma_set_transfer_params()
1115 edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); in edma_set_transfer_params()
1117 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); in edma_set_transfer_params()
1118 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); in edma_set_transfer_params()
1157 unsigned ctlr; in edma_unlink() local
1159 ctlr = EDMA_CTLR(from); in edma_unlink()
1162 if (from >= edma_cc[ctlr]->num_slots) in edma_unlink()
1164 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); in edma_unlink()
1184 unsigned ctlr; in edma_write_slot() local
1186 ctlr = EDMA_CTLR(slot); in edma_write_slot()
1189 if (slot >= edma_cc[ctlr]->num_slots) in edma_write_slot()
1191 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, in edma_write_slot()
1206 unsigned ctlr; in edma_read_slot() local
1208 ctlr = EDMA_CTLR(slot); in edma_read_slot()
1211 if (slot >= edma_cc[ctlr]->num_slots) in edma_read_slot()
1213 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), in edma_read_slot()
1231 unsigned ctlr; in edma_pause() local
1233 ctlr = EDMA_CTLR(channel); in edma_pause()
1236 if (channel < edma_cc[ctlr]->num_channels) { in edma_pause()
1239 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); in edma_pause()
1252 unsigned ctlr; in edma_resume() local
1254 ctlr = EDMA_CTLR(channel); in edma_resume()
1257 if (channel < edma_cc[ctlr]->num_channels) { in edma_resume()
1260 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); in edma_resume()
1267 unsigned ctlr; in edma_trigger_channel() local
1270 ctlr = EDMA_CTLR(channel); in edma_trigger_channel()
1274 edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask); in edma_trigger_channel()
1277 edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5))); in edma_trigger_channel()
1295 unsigned ctlr; in edma_start() local
1297 ctlr = EDMA_CTLR(channel); in edma_start()
1300 if (channel < edma_cc[ctlr]->num_channels) { in edma_start()
1305 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { in edma_start()
1307 edma_shadow0_read_array(ctlr, SH_ESR, j)); in edma_start()
1308 edma_shadow0_write_array(ctlr, SH_ESR, j, mask); in edma_start()
1314 edma_shadow0_read_array(ctlr, SH_ER, j)); in edma_start()
1316 edma_write_array(ctlr, EDMA_ECR, j, mask); in edma_start()
1317 edma_write_array(ctlr, EDMA_EMCR, j, mask); in edma_start()
1319 edma_shadow0_write_array(ctlr, SH_SECR, j, mask); in edma_start()
1320 edma_shadow0_write_array(ctlr, SH_EESR, j, mask); in edma_start()
1322 edma_shadow0_read_array(ctlr, SH_EER, j)); in edma_start()
1341 unsigned ctlr; in edma_stop() local
1343 ctlr = EDMA_CTLR(channel); in edma_stop()
1346 if (channel < edma_cc[ctlr]->num_channels) { in edma_stop()
1350 edma_shadow0_write_array(ctlr, SH_EECR, j, mask); in edma_stop()
1351 edma_shadow0_write_array(ctlr, SH_ECR, j, mask); in edma_stop()
1352 edma_shadow0_write_array(ctlr, SH_SECR, j, mask); in edma_stop()
1353 edma_write_array(ctlr, EDMA_EMCR, j, mask); in edma_stop()
1356 edma_shadow0_read_array(ctlr, SH_EER, j)); in edma_stop()
1380 unsigned ctlr; in edma_clean_channel() local
1382 ctlr = EDMA_CTLR(channel); in edma_clean_channel()
1385 if (channel < edma_cc[ctlr]->num_channels) { in edma_clean_channel()
1390 edma_read_array(ctlr, EDMA_EMR, j)); in edma_clean_channel()
1391 edma_shadow0_write_array(ctlr, SH_ECR, j, mask); in edma_clean_channel()
1393 edma_write_array(ctlr, EDMA_EMCR, j, mask); in edma_clean_channel()
1395 edma_shadow0_write_array(ctlr, SH_SECR, j, mask); in edma_clean_channel()
1396 edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); in edma_clean_channel()
1408 unsigned ctlr; in edma_clear_event() local
1410 ctlr = EDMA_CTLR(channel); in edma_clear_event()
1413 if (channel >= edma_cc[ctlr]->num_channels) in edma_clear_event()
1416 edma_write(ctlr, EDMA_ECR, BIT(channel)); in edma_clear_event()
1418 edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); in edma_clear_event()
1432 unsigned ctlr; in edma_assign_channel_eventq() local
1434 ctlr = EDMA_CTLR(channel); in edma_assign_channel_eventq()
1437 if (channel >= edma_cc[ctlr]->num_channels) in edma_assign_channel_eventq()
1442 eventq_no = edma_cc[ctlr]->default_queue; in edma_assign_channel_eventq()
1443 if (eventq_no >= edma_cc[ctlr]->num_tc) in edma_assign_channel_eventq()
1446 map_dmach_queue(ctlr, channel, eventq_no); in edma_assign_channel_eventq()