265 		void (*callback)(unsigned channel, unsigned short ch_status,
329 	void (*callback)(unsigned channel, u16 ch_status, void *data),  in setup_dma_interrupt()  argument
395 		u32 channel;  in dma_irq_handler()  local
403 			channel = (bank << 5) | slot;  in dma_irq_handler()
407 			if (edma_cc[ctlr]->intr_data[channel].callback)  in dma_irq_handler()
408 				edma_cc[ctlr]->intr_data[channel].callback(  in dma_irq_handler()
409 					EDMA_CTLR_CHAN(ctlr, channel),  in dma_irq_handler()
411 					edma_cc[ctlr]->intr_data[channel].data);  in dma_irq_handler()
646 int edma_alloc_channel(int channel,  in edma_alloc_channel()  argument
647 		void (*callback)(unsigned channel, u16 ch_status, void *data),  in edma_alloc_channel()  argument
668 	if (channel >= 0) {  in edma_alloc_channel()
669 		ctlr = EDMA_CTLR(channel);  in edma_alloc_channel()
670 		channel = EDMA_CHAN_SLOT(channel);  in edma_alloc_channel()
673 	if (channel < 0) {  in edma_alloc_channel()
675 			channel = 0;  in edma_alloc_channel()
677 				channel = find_next_bit(edma_cc[i]->edma_unused,  in edma_alloc_channel()
679 						channel);  in edma_alloc_channel()
680 				if (channel == edma_cc[i]->num_channels)  in edma_alloc_channel()
682 				if (!test_and_set_bit(channel,  in edma_alloc_channel()
688 				channel++;  in edma_alloc_channel()
695 	} else if (channel >= edma_cc[ctlr]->num_channels) {  in edma_alloc_channel()
697 	} else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {  in edma_alloc_channel()
702 	edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));  in edma_alloc_channel()
705 	edma_stop(EDMA_CTLR_CHAN(ctlr, channel));  in edma_alloc_channel()
706 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),  in edma_alloc_channel()
710 		setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),  in edma_alloc_channel()
713 	map_dmach_queue(ctlr, channel, eventq_no);  in edma_alloc_channel()
715 	return EDMA_CTLR_CHAN(ctlr, channel);  in edma_alloc_channel()
731 void edma_free_channel(unsigned channel)  in edma_free_channel()  argument
735 	ctlr = EDMA_CTLR(channel);  in edma_free_channel()
736 	channel = EDMA_CHAN_SLOT(channel);  in edma_free_channel()
738 	if (channel >= edma_cc[ctlr]->num_channels)  in edma_free_channel()
741 	setup_dma_interrupt(channel, NULL, NULL);  in edma_free_channel()
744 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),  in edma_free_channel()
746 	clear_bit(channel, edma_cc[ctlr]->edma_inuse);  in edma_free_channel()
1229 void edma_pause(unsigned channel)  in edma_pause()  argument
1233 	ctlr = EDMA_CTLR(channel);  in edma_pause()
1234 	channel = EDMA_CHAN_SLOT(channel);  in edma_pause()
1236 	if (channel < edma_cc[ctlr]->num_channels) {  in edma_pause()
1237 		unsigned int mask = BIT(channel & 0x1f);  in edma_pause()
1239 		edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);  in edma_pause()
1250 void edma_resume(unsigned channel)  in edma_resume()  argument
1254 	ctlr = EDMA_CTLR(channel);  in edma_resume()
1255 	channel = EDMA_CHAN_SLOT(channel);  in edma_resume()
1257 	if (channel < edma_cc[ctlr]->num_channels) {  in edma_resume()
1258 		unsigned int mask = BIT(channel & 0x1f);  in edma_resume()
1260 		edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);  in edma_resume()
1265 int edma_trigger_channel(unsigned channel)  in edma_trigger_channel()  argument
1270 	ctlr = EDMA_CTLR(channel);  in edma_trigger_channel()
1271 	channel = EDMA_CHAN_SLOT(channel);  in edma_trigger_channel()
1272 	mask = BIT(channel & 0x1f);  in edma_trigger_channel()
1274 	edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);  in edma_trigger_channel()
1276 	pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),  in edma_trigger_channel()
1277 		 edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));  in edma_trigger_channel()
1293 int edma_start(unsigned channel)  in edma_start()  argument
1297 	ctlr = EDMA_CTLR(channel);  in edma_start()
1298 	channel = EDMA_CHAN_SLOT(channel);  in edma_start()
1300 	if (channel < edma_cc[ctlr]->num_channels) {  in edma_start()
1301 		int j = channel >> 5;  in edma_start()
1302 		unsigned int mask = BIT(channel & 0x1f);  in edma_start()
1305 		if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {  in edma_start()
1339 void edma_stop(unsigned channel)  in edma_stop()  argument
1343 	ctlr = EDMA_CTLR(channel);  in edma_stop()
1344 	channel = EDMA_CHAN_SLOT(channel);  in edma_stop()
1346 	if (channel < edma_cc[ctlr]->num_channels) {  in edma_stop()
1347 		int j = channel >> 5;  in edma_stop()
1348 		unsigned int mask = BIT(channel & 0x1f);  in edma_stop()
1378 void edma_clean_channel(unsigned channel)  in edma_clean_channel()  argument
1382 	ctlr = EDMA_CTLR(channel);  in edma_clean_channel()
1383 	channel = EDMA_CHAN_SLOT(channel);  in edma_clean_channel()
1385 	if (channel < edma_cc[ctlr]->num_channels) {  in edma_clean_channel()
1386 		int j = (channel >> 5);  in edma_clean_channel()
1387 		unsigned int mask = BIT(channel & 0x1f);  in edma_clean_channel()
1406 void edma_clear_event(unsigned channel)  in edma_clear_event()  argument
1410 	ctlr = EDMA_CTLR(channel);  in edma_clear_event()
1411 	channel = EDMA_CHAN_SLOT(channel);  in edma_clear_event()
1413 	if (channel >= edma_cc[ctlr]->num_channels)  in edma_clear_event()
1415 	if (channel < 32)  in edma_clear_event()
1416 		edma_write(ctlr, EDMA_ECR, BIT(channel));  in edma_clear_event()
1418 		edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));  in edma_clear_event()
1430 void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)  in edma_assign_channel_eventq()  argument
1434 	ctlr = EDMA_CTLR(channel);  in edma_assign_channel_eventq()
1435 	channel = EDMA_CHAN_SLOT(channel);  in edma_assign_channel_eventq()
1437 	if (channel >= edma_cc[ctlr]->num_channels)  in edma_assign_channel_eventq()
1446 	map_dmach_queue(ctlr, channel, eventq_no);  in edma_assign_channel_eventq()