Lines Matching refs:CLK_A
171 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
172 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
173 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
174 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
175 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
176 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
177 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
181 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
184 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
185 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
186 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
187 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
189 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
190 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
191 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
192 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
197 txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>;
198 txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>;
199 txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>;
200 txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>;
201 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
202 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
205 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
206 rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>;
207 rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>;
208 rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>;
209 rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>;
211 rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
212 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
215 clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
437 txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
438 txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
439 txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
443 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
444 txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
450 rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
451 rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
452 rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
453 rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
454 rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
455 rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
456 rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
468 txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>;
469 txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>;
470 txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>;
473 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
478 rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>;
479 rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>;
480 rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>;
481 rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>;
482 rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>;
483 rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>;
485 clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>;