Lines Matching refs:errata

1020 	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1029 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1038 	bool "ARM errata: Stale prediction on replaced interworking branch"
1054 	bool "ARM errata: Processor deadlock when a false hazard is created"
1068 	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1081 	bool "ARM errata: DMB operation may be faulty"
1094 	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1109 	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1120 	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1132 	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1146 	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1157 	bool "ARM errata: possible faulty MMU translations following an ASID switch"
1168 	bool "ARM errata: no automatic Store Buffer drain"
1179 	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1191 	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1205        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1215 	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1225 	bool "ARM errata: incorrect instructions may be executed from loop buffer"