Lines Matching refs:C
112 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
115 static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
116 [C(L1D)] = {
117 [C(OP_READ)] = {
118 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
119 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
121 [C(OP_WRITE)] = {
122 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
123 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
125 [C(OP_PREFETCH)] = {
126 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
127 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
130 [C(L1I)] = {
131 [C(OP_READ)] = {
132 [C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS,
133 [C(RESULT_MISS)] = PERF_COUNT_ARC_ICM,
135 [C(OP_WRITE)] = {
136 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
137 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
139 [C(OP_PREFETCH)] = {
140 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
141 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
144 [C(LL)] = {
145 [C(OP_READ)] = {
146 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
147 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
149 [C(OP_WRITE)] = {
150 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
151 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
153 [C(OP_PREFETCH)] = {
154 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
155 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
158 [C(DTLB)] = {
159 [C(OP_READ)] = {
160 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
161 [C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB,
164 [C(OP_WRITE)] = {
165 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
166 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
168 [C(OP_PREFETCH)] = {
169 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
170 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
173 [C(ITLB)] = {
174 [C(OP_READ)] = {
175 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
176 [C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB,
178 [C(OP_WRITE)] = {
179 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
180 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
182 [C(OP_PREFETCH)] = {
183 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
184 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
187 [C(BPU)] = {
188 [C(OP_READ)] = {
189 [C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
190 [C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES,
192 [C(OP_WRITE)] = {
193 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
194 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
196 [C(OP_PREFETCH)] = {
197 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
198 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
201 [C(NODE)] = {
202 [C(OP_READ)] = {
203 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
204 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
206 [C(OP_WRITE)] = {
207 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
208 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
210 [C(OP_PREFETCH)] = {
211 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
212 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,