180 	volatile unsigned long *csr;  in tsunami_pci_tbi()  local
185 	csr = &pchip->tlbia.csr;  in tsunami_pci_tbi()
187 		csr = &pchip->tlbiv.csr;  in tsunami_pci_tbi()
193 	*csr = value;  in tsunami_pci_tbi()
195 	*csr;  in tsunami_pci_tbi()
226 	TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */  in tsunami_probe_write()
230 	if (TSUNAMI_cchip->misc.csr & (1L << 28)) {  in tsunami_probe_write()
231 		int source = (TSUNAMI_cchip->misc.csr >> 29) & 7;  in tsunami_probe_write()
232 		TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */  in tsunami_probe_write()
250 	if (tsunami_probe_read(&pchip->pctl.csr) == 0)  in tsunami_init_one_pchip()
293 	saved_config[index].wsba[0] = pchip->wsba[0].csr;  in tsunami_init_one_pchip()
294 	saved_config[index].wsm[0] = pchip->wsm[0].csr;  in tsunami_init_one_pchip()
295 	saved_config[index].tba[0] = pchip->tba[0].csr;  in tsunami_init_one_pchip()
297 	saved_config[index].wsba[1] = pchip->wsba[1].csr;  in tsunami_init_one_pchip()
298 	saved_config[index].wsm[1] = pchip->wsm[1].csr;  in tsunami_init_one_pchip()
299 	saved_config[index].tba[1] = pchip->tba[1].csr;  in tsunami_init_one_pchip()
301 	saved_config[index].wsba[2] = pchip->wsba[2].csr;  in tsunami_init_one_pchip()
302 	saved_config[index].wsm[2] = pchip->wsm[2].csr;  in tsunami_init_one_pchip()
303 	saved_config[index].tba[2] = pchip->tba[2].csr;  in tsunami_init_one_pchip()
305 	saved_config[index].wsba[3] = pchip->wsba[3].csr;  in tsunami_init_one_pchip()
306 	saved_config[index].wsm[3] = pchip->wsm[3].csr;  in tsunami_init_one_pchip()
307 	saved_config[index].tba[3] = pchip->tba[3].csr;  in tsunami_init_one_pchip()
332 	pchip->wsba[0].csr = hose->sg_isa->dma_base | 3;  in tsunami_init_one_pchip()
333 	pchip->wsm[0].csr  = (hose->sg_isa->size - 1) & 0xfff00000;  in tsunami_init_one_pchip()
334 	pchip->tba[0].csr  = virt_to_phys(hose->sg_isa->ptes);  in tsunami_init_one_pchip()
336 	pchip->wsba[1].csr = hose->sg_pci->dma_base | 3;  in tsunami_init_one_pchip()
337 	pchip->wsm[1].csr  = (hose->sg_pci->size - 1) & 0xfff00000;  in tsunami_init_one_pchip()
338 	pchip->tba[1].csr  = virt_to_phys(hose->sg_pci->ptes);  in tsunami_init_one_pchip()
340 	pchip->wsba[2].csr = 0x80000000 | 1;  in tsunami_init_one_pchip()
341 	pchip->wsm[2].csr  = (0x80000000 - 1) & 0xfff00000;  in tsunami_init_one_pchip()
342 	pchip->tba[2].csr  = 0;  in tsunami_init_one_pchip()
344 	pchip->wsba[3].csr = 0;  in tsunami_init_one_pchip()
347 	pchip->pctl.csr |= pctl_m_mwin;  in tsunami_init_one_pchip()
393 	printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr);  in tsunami_init_arch()
394 	printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr);  in tsunami_init_arch()
395 	printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr);  in tsunami_init_arch()
396 	printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr);  in tsunami_init_arch()
397 	printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr);  in tsunami_init_arch()
398 	printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr);  in tsunami_init_arch()
399 	printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr);  in tsunami_init_arch()
400 	printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr);  in tsunami_init_arch()
403 	printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr);  in tsunami_init_arch()
404 	printk("%s: CSR_STR 0x%lx\n", __func__, TSUNAMI_dchip->str.csr);  in tsunami_init_arch()
405 	printk("%s: CSR_DREV 0x%lx\n", __func__, TSUNAMI_dchip->drev.csr);  in tsunami_init_arch()
414 	if (TSUNAMI_cchip->csc.csr & 1L<<14)  in tsunami_init_arch()
424 	pchip->wsba[0].csr = saved_config[index].wsba[0];  in tsunami_kill_one_pchip()
425 	pchip->wsm[0].csr = saved_config[index].wsm[0];  in tsunami_kill_one_pchip()
426 	pchip->tba[0].csr = saved_config[index].tba[0];  in tsunami_kill_one_pchip()
428 	pchip->wsba[1].csr = saved_config[index].wsba[1];  in tsunami_kill_one_pchip()
429 	pchip->wsm[1].csr = saved_config[index].wsm[1];  in tsunami_kill_one_pchip()
430 	pchip->tba[1].csr = saved_config[index].tba[1];  in tsunami_kill_one_pchip()
432 	pchip->wsba[2].csr = saved_config[index].wsba[2];  in tsunami_kill_one_pchip()
433 	pchip->wsm[2].csr = saved_config[index].wsm[2];  in tsunami_kill_one_pchip()
434 	pchip->tba[2].csr = saved_config[index].tba[2];  in tsunami_kill_one_pchip()
436 	pchip->wsba[3].csr = saved_config[index].wsba[3];  in tsunami_kill_one_pchip()
437 	pchip->wsm[3].csr = saved_config[index].wsm[3];  in tsunami_kill_one_pchip()
438 	pchip->tba[3].csr = saved_config[index].tba[3];  in tsunami_kill_one_pchip()
445 	if (TSUNAMI_cchip->csc.csr & 1L<<14)  in tsunami_kill_arch()
452 	pchip->perror.csr;  in tsunami_pci_clr_err_1()
453 	pchip->perror.csr = 0x040;  in tsunami_pci_clr_err_1()
455 	pchip->perror.csr;  in tsunami_pci_clr_err_1()
464 	if (TSUNAMI_cchip->csc.csr & 1L<<14)  in tsunami_pci_clr_err()