62 	q = ev7csr->csr;  in read_ev7_csr()
74 	ev7csr->csr = q;  in write_ev7_csr()
179 		csrs->POx_ERR_SUM.csr = -1UL;  in io7_clear_errors()
180 		csrs->POx_TLB_ERR.csr = -1UL;  in io7_clear_errors()
181 		csrs->POx_SPL_COMPLT.csr = -1UL;  in io7_clear_errors()
182 		csrs->POx_TRANS_SUM.csr = -1UL;  in io7_clear_errors()
190 	p7csrs->PO7_ERROR_SUM.csr = -1UL;  in io7_clear_errors()
191 	p7csrs->PO7_UNCRR_SYM.csr = -1UL;  in io7_clear_errors()
192 	p7csrs->PO7_CRRCT_SYM.csr = -1UL;  in io7_clear_errors()
263 		io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr;  in io7_init_hose()
264 		io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr;  in io7_init_hose()
265 		io7_port->saved_tbase[i] = csrs->POx_TBASE[i].csr;  in io7_init_hose()
288 	csrs->POx_WBASE[0].csr =   in io7_init_hose()
290 	csrs->POx_WMASK[0].csr = (hose->sg_isa->size - 1) & wbase_m_addr;  in io7_init_hose()
291 	csrs->POx_TBASE[0].csr = virt_to_phys(hose->sg_isa->ptes);  in io7_init_hose()
296 	csrs->POx_WBASE[1].csr = __direct_map_base | wbase_m_ena;  in io7_init_hose()
297 	csrs->POx_WMASK[1].csr = (__direct_map_size - 1) & wbase_m_addr;  in io7_init_hose()
298 	csrs->POx_TBASE[1].csr = 0;  in io7_init_hose()
306 	csrs->POx_WBASE[2].csr =   in io7_init_hose()
308 	csrs->POx_WMASK[2].csr = (hose->sg_pci->size - 1) & wbase_m_addr;  in io7_init_hose()
309 	csrs->POx_TBASE[2].csr = virt_to_phys(hose->sg_pci->ptes);  in io7_init_hose()
314 	csrs->POx_WBASE[3].csr = 0;  in io7_init_hose()
319 	csrs->POx_CTRL.csr &= ~(1UL << 61);  in io7_init_hose()
323 	csrs->POx_MSK_HEI.csr &= ~(3UL << 14);  in io7_init_hose()
348 		if (csrs->POx_CACHE_CTL.csr == 8) {  in marvel_init_io7()
607 	csrs->POx_SG_TBIA.csr = 0;  in marvel_pci_tbi()
609 	csrs->POx_SG_TBIA.csr;  in marvel_pci_tbi()
963 	agp_pll = io7->csrs->POx_RST[IO7_AGP_PORT].csr;  in marvel_agp_configure()
1009 	csrs->AGP_CMD.csr = agp->mode.lw;  in marvel_agp_configure()
1130 	agp->capability.lw = csrs->AGP_STAT.csr;  in marvel_agp_info()
1136 	agp->mode.lw = csrs->AGP_CMD.csr;  in marvel_agp_info()