47 #define vuip	volatile unsigned int  *  macro
137 	stat0 = *(vuip)APECS_IOC_DCSR;  in conf_read()
138 	*(vuip)APECS_IOC_DCSR = stat0;  in conf_read()
144 		haxr2 = *(vuip)APECS_IOC_HAXR2;  in conf_read()
146 		*(vuip)APECS_IOC_HAXR2 = haxr2 | 1;  in conf_read()
158 	asm volatile("ldl %0,%1; mb; mb" : "=r"(value) : "m"(*(vuip)addr)  in conf_read()
179 	stat0 = *(vuip)APECS_IOC_DCSR;  in conf_read()
190 		*(vuip)APECS_IOC_DCSR = stat0;  in conf_read()
199 		*(vuip)APECS_IOC_HAXR2 = haxr2 & ~1;  in conf_read()
217 	stat0 = *(vuip)APECS_IOC_DCSR;  in conf_write()
218 	*(vuip)APECS_IOC_DCSR = stat0;  in conf_write()
223 		haxr2 = *(vuip)APECS_IOC_HAXR2;  in conf_write()
225 		*(vuip)APECS_IOC_HAXR2 = haxr2 | 1;  in conf_write()
233 	*(vuip)addr = value;  in conf_write()
249 	stat0 = *(vuip)APECS_IOC_DCSR;  in conf_write()
259 		*(vuip)APECS_IOC_DCSR = stat0;  in conf_write()
267 		*(vuip)APECS_IOC_HAXR2 = haxr2 & ~1;  in conf_write()
353 	*(vuip)APECS_IOC_PB1R = __direct_map_base | 0x00080000;  in apecs_init_arch()
354 	*(vuip)APECS_IOC_PM1R = (__direct_map_size - 1) & 0xfff00000U;  in apecs_init_arch()
355 	*(vuip)APECS_IOC_TB1R = 0;  in apecs_init_arch()
357 	*(vuip)APECS_IOC_PB2R = hose->sg_isa->dma_base | 0x000c0000;  in apecs_init_arch()
358 	*(vuip)APECS_IOC_PM2R = (hose->sg_isa->size - 1) & 0xfff00000;  in apecs_init_arch()
359 	*(vuip)APECS_IOC_TB2R = virt_to_phys(hose->sg_isa->ptes) >> 1;  in apecs_init_arch()
369 	*(vuip)APECS_IOC_HAXR2 = 0;  in apecs_init_arch()
378 	jd = *(vuip)APECS_IOC_DCSR;  in apecs_pci_clr_err()
380 		*(vuip)APECS_IOC_SEAR;  in apecs_pci_clr_err()
381 		*(vuip)APECS_IOC_DCSR = jd | 0xffe1L;  in apecs_pci_clr_err()
383 		*(vuip)APECS_IOC_DCSR;  in apecs_pci_clr_err()
385 	*(vuip)APECS_IOC_TBIA = (unsigned int)APECS_IOC_TBIA;  in apecs_pci_clr_err()
387 	*(vuip)APECS_IOC_TBIA;  in apecs_pci_clr_err()