Lines Matching refs:IP

51 again, pre-designed building blocks, IP cores, are often used. These are the
52 FPGA parallels of library functions. IP cores may implement certain
79 Xillybus is an IP core and a Linux driver. Together, they form a kit for
88 IP core. Rather, the IP core is configured and built based upon a
91 Xillybus presents independent data streams, which resemble pipes or TCP/IP
96 There may be more than a hundred of these streams on a single IP core, but
99 In order to ease the deployment of the Xillybus IP core, it contains a simple
103 driver is used to work out of the box with any Xillybus IP core.
116 names of these files depend on the IP core that is loaded in the FPGA (see
136   pieces of data sent across (like TCP/IP) by autoflushing.
145 Xillybus pipes are configured (on the IP core) to be either synchronous or
201 (IP core) is built. They are fetched from the IDT (the data structure which
272 FPGA, the Xillybus IP core writes it to one of the DMA buffers. When the
280 This is not good enough for creating a TCP/IP-like stream: If the data flow
329 loads and their attributes depend on the Xillybus IP core in the FPGA. During
379 These messages are used only to support poll() and select(). The IP core can