Lines Matching refs:counter

102  for (N-1)/2 counts.  Only even values are latched by the counter, so odd
106 Mode 4: Software Strobe.  After programming this mode and loading the counter,
107  the output remains high until the counter reaches zero.  Then the output
108  goes low for 1 clock cycle and returns high.  The counter is not reloaded.
111 Mode 5: Hardware Strobe.  After programming and loading the counter, the
113  (which does not stop if the gate is lowered).  When the counter reaches zero,
114  the output goes low for 1 clock cycle and then returns high.  The counter is
118 command port, 0x43 is used to set the counter and mode for each of the three
131 	additional commands ignored until counter is read;
156 1101 - General counter latch
164 	Latch combination of counter mode into corresponding ports
314 The TSC or time stamp counter is relatively simple in theory; it counts
322 was only possible to write the low 32-bits of the 64-bit counter, and the upper
323 32-bits of the counter were cleared.  Now, however, on Intel processors family
507 As the highest precision time source available, the cycle counter of the CPU
512 definition, the counter, once read is already old.  However, it is also
513 possible for the counter to be read ahead of the actual use of the result.
522 accurate time stamp counter reading may therefore not always be available, and