Lines Matching refs:that

11 specific per cpu base and encode that operation in the instruction
14 This means that there are no atomicity issues between the calculation of
16 necessary to disable preemption or interrupts to ensure that the
21 processors have special lower latency instructions that can operate
30 processor should be accessing that variable and therefore there are no
33 Please note that accesses by remote processors to a per cpu area are
82 from that address which occurs with the per cpu operations. Before
106 Note that these operations can only be used on per cpu data that is
108 surrounding code this_cpu_inc() will only guarantee that one of the
110 guarantee that the OS will not move the process directly before or
111 after the this_cpu instruction is executed. In general this means that
114 that is of interest.
119 variables no concurrent cache line updates take place. The price that
130 of the per cpu variable that belongs to the currently executing
131 processor.  this_cpu_ptr avoids multiple steps that the common
136 Note that this operation is usually used in a code segment when
147 area. They do not have addresses although they look like that in the
158 In the context of per cpu operations the above implies that x is a per
212 these per cpu local operations. In that case the operation must be
213 replaced by code that disables interrupts, then does the operations
214 that are guaranteed to be atomic and then re-enable interrupts. Doing
217 disable interrupts. For that purpose the following __this_cpu operations
244 Will increment x and will not fall-back to code that disables
245 interrupts on platforms that cannot accomplish atomicity through
272 and that is frequently done to summarize counters. Remote write access
289 This makes it explicit that we are getting ready to access a percpu
303 One example that illustrates some concerns with write operations is
304 the following scenario that occurs because two per cpu variables
320 to update field b. Care should be taken that such simultaneous accesses to
326 mind that a remote write will evict the cache line from the processor
327 that most likely will access it. If the processor wakes up and finds a