Lines Matching refs:SSP

1 PXA2xx SPI on SSP driver HOWTO
7 - Support for any PXA2xx SSP
8 - SSP PIO and SSP DMA data transfers.
31 corresponding SSP peripheral block in the "Clock Enable Register (CKEN"). See
37 The "pxa2xx_spi_master.enable_dma" field informs the driver that SSP DMA should
67 	.id = 2, /* Bus number, MUST MATCH SSP number 1..n */
106 used to configure the SSP hardware fifo.  These fields are critical to the
117 the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
118 to determine the correct value. An SSP configured for byte-wide transfers would
123 trailing bytes in the SSP receiver fifo.  The correct value for this field is
125 slave device.  Please note that the PXA2xx SSP 1 does not support trailing byte
128 The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
129 into internal loopback mode.  In this mode the SSP controller internally
135 NULL, the pxa2xx_spi master controller driver assumes that the SSP port is
169 	.tx_threshold = 8, /* SSP hardward FIFO threshold */
170 	.rx_threshold = 8, /* SSP hardward FIFO threshold */
177 	.tx_threshold = 8, /* SSP hardward FIFO threshold */
178 	.rx_threshold = 8, /* SSP hardward FIFO threshold */
187 		.max_speed_hz = 3686400, /* Run SSP as fast a possbile */
196 		.max_speed_hz = 3686400, /* Run SSP as fast a possbile */