Lines Matching refs:that

17 to freeze a device that is causing errors in order to limit the possibility
20 There is thus, in HW, a table of PE states that contains a pair of "frozen"
25 return all 1's value. MSIs are also blocked. There's a bit more state that
26 captures things like the details of the error that caused the freeze etc., but
27 that's not critical.
33 (IODA2).  Keep in mind that this is all per PHB (PCI host bridge).  Each PHB
34 is a completely separate HW entity that replicates the entire logic, so has
44     memory but accessed in HW by the chip) that provides a direct
48     - For DMA we then provide an entire address space for each PE that can
59       the RTT to "authorize" the device to emit that specific interrupt.
78 	32-bit PCIe accesses.  We configure that window at boot from FW and
84 	ignores that however and will forward in that space if we try).
93     onto a segment alignment/granularity so that the space behind a bridge
97     but that would mean using a completely different address allocation
117     We have code (fairly new compared to the M32 stuff) that exploits that
121     that has been assigned by FW for the PHB (about 64GB, ignore the space
132       update the M32 PE# for the devices that use both 32-bit and 64-bit
138       that only works for PCIe error messages (typically used so that if
140       SW.  We lose a bit of effectiveness of EEH in that case, but that's
142       other ones for that "domain".  We thus introduce the concept of
144       PEs" that are used for the remaining M64 segments.
147     PE" mode to overlay over specific BARs to work around some of that, for
170     1MB VF BAR0, the address in that VF BAR sets the base of an 8MB region.
172     is a BAR0 for one of the VFs.  Note that even though the VF BAR
180     window with 1MB segments.  VF BARs that are 1MB or larger could be
184     they are different sizes, the entire window has to be small enough that
200     and different segment sizes.  If we have VFs that each have a 1MB BAR
208   segments/PEs inside that M64 window.
246   space doesn't need that much, as shown in Figure 1.1:
264   Allocating the extra space ensures that the entire M64 window will be
266   available for other devices.  Note that this only expands the space
268   respond to segments [0, total_VFs - 1].  There's nothing in hardware that
273 The PCIe SR-IOV spec requires that the base of the VF(n) BAR space be
277 window, we can set the PE# by updating the table that translates segments