Lines Matching refs:SPI

122 For example, say that we have a group of pins dealing with an SPI interface
436 In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
440 we cannot use the SPI port and I2C port at the same time. However in the inside
441 of the package the silicon performing the SPI logic can alternatively be routed
447 { A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
452 contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
812                        |               +- SPI
837                        |               +- SPI
846 e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
1358 an SPI port from one set of pins to another set of pins. Say for example for
1361 "Advanced mapping" above. So that for an SPI device, we have two states named