Lines Matching refs:it

28 to receive data from the hardware. A "full" descriptor has data in it,
30 descriptor is neither empty or full; it is simply not ready. It may
31 not even have a data buffer in it, or is otherwise unusable.
44 marks it full, and advances the GDACTDPA by one.  Thus, when there is
45 flowing RX traffic, every descr behind it should be marked "full",
46 and everything in front of it should be "empty".  If the hardware
47 discovers that the current descr is not empty, it will signal an
52 descr. The OS will process this descr, and then mark it "not-in-use",
55 all of those behind it should be "not-in-use". When RX traffic is not
64 dma-mapping it so as to make it visible to the hardware. The OS will
67 be "not-in-use", and everything behind it should be "empty". If no
70 "empty", and it will halt processing.
92 head and tail are pointing at 20, because it has not yet been emptied.
126 When the OS finally has a chance to run, it will empty out the RX ring.
127 In particular, it will clear the descriptor on which the hardware had
129 descriptor is invalid, it will not restart at that descriptor; instead
130 it will restart at the next descr. This potentially will lead to a
171 of the RX chain seems to show it is empty, then it is probable that
188 the TX ring quicker than the device can drain it. Once the ring
200 can fill it.