Lines Matching refs:in

5 Some notes about Marvell's NAND controller available in PXA and Armada 370/XP
11 The controller has a 2176 bytes FIFO buffer. Therefore, in order to support
16 we'll have this layout in the pages:
23 buffer with this layout (in the 4 KiB page case):
36 So, in order to achieve reading (for instance), we issue several READ0 commands
45 The controller has built-in hardware ECC capabilities. In addition it is
56 spare, and then the ECC controller will read/write the ECC code (30B in
65 So in Hamming mode, a 2048B page will have a 24B ECC.
68 write in multiples of 8-bytes, because the data buffer is 64-bits.
73 Because of the above scheme, and because the "spare" OOB is really located in
75 data area. In other words, in order to read the OOB (aka READOOB), the entire
78 In the same sense, in order to write to the spare OOB the driver has to write
84 Given the ECC BCH requires to layout the device's pages in a split
101 searched within the 'data' region, and not in the usual OOB region.
107 For this reason, marking the block as bad in the OOB is explicitly
108 disabled by using the NAND_BBT_NO_OOB_BBM option in the driver. The rationale
109 for this is that there's no point in marking a block as bad, because good
110 blocks are also 'marked as bad' (in the OOB BBM sense) under normal usage.