Lines Matching refs:sequence

113 For example, consider the following sequence of events:
147 As a further example, consider this sequence of events:
156 the address retrieved from P by CPU 2.  At the end of the sequence, any of the
214      the CPU will only issue the following sequence of memory operations:
298 		either an object of scalar type, or a maximal sequence
352      A CPU can be viewed as committing a sequence of store operations to the
354      occur in the sequence _before_ all the stores after the write barrier.
377      load touches one of a sequence of stores from another CPU, then by the
516 following sequence of events:
528 sequence, Q must be either &A or &B, and that:
889 Consider the following sequence of events:
900 This sequence of events is committed to the memory coherence system in an order
927 loads.  Consider the following sequence of events:
1014 following sequence of events:
1929 The following sequence of events is acceptable:
1963 Firstly, the sleeper normally follows something like this sequence of events:
1989 The whole sequence above is available in various canned forms, all of which
2025 is actually awakened.  To see this, consider the following sequence of
2115 three CPUs; then should the following sequence of events occur:
2300 In other words, it has to perform this sequence of events:
2318 Consider then what might happen to the above sequence of events:
2625 A CPU may also discard any instruction sequence that winds up having no
2881 instruction before moving on to the next one, leading to a definite sequence of
2898      at the wrong time in the expected sequence of events;
2940 The code above may cause the CPU to generate the full sequence of memory
2945 in that order, but, without intervention, the sequence may have almost any
2954 The compiler may also combine, discard or defer elements of the sequence before