Lines Matching refs:pair

457      pair is -not- guaranteed to act as a full memory barrier.  However, after
625 Control dependencies pair normally with other types of barriers.
817   (*) Control dependencies pair normally with other types of barriers.
829 General barriers pair with each other, though they also pair with most
831 pairs with a release barrier, but both may also pair with other barriers,
1299 The key point is that although CPU 2's read barrier orders its pair
1603      assignment statements as a pair of 32-bit loads followed by a pair
1843 pair to produce a full barrier, the ACQUIRE can be followed by an
2114 Consider the following: the system has a pair of spinlocks (M) and (Q), and
2706 Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2707 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2772 The above pair of reads may then fail to happen in the expected order, as the