Lines Matching refs:operations
12 - Device operations.
47 - Atomic operations.
101 Each CPU executes a program that generates memory access operations. In the
103 perform the memory operations in any order it likes, provided program causality
108 So in the above diagram, the effects of the memory operations performed by a
109 CPU are perceived by the rest of the system as the operations cross the
199 the CPU will issue the following memory operations:
214 the CPU will only issue the following sequence of memory operations:
321 As can be seen above, independent memory operations are effectively performed
327 ordering over the memory operations on either side of the barrier.
331 deferral and combination of memory operations; speculative loads; speculative
344 A write memory barrier gives a guarantee that all the STORE operations
346 operations specified after the barrier with respect to the other
352 A CPU can be viewed as committing a sequence of store operations to the
399 LOAD operations specified before the barrier will appear to happen before
400 all the LOAD operations specified after the barrier with respect to the
416 operations specified before the barrier will appear to happen before all
417 the LOAD and STORE operations specified after the barrier with respect to
428 (5) ACQUIRE operations.
431 operations after the ACQUIRE operation will appear to happen after the
433 ACQUIRE operations include LOCK operations and smp_load_acquire()
434 operations.
436 Memory operations that occur before an ACQUIRE operation may appear to
443 (6) RELEASE operations.
446 memory operations before the RELEASE operation will appear to happen
448 system. RELEASE operations include UNLOCK operations and
449 smp_store_release() operations.
451 Memory operations that occur after a RELEASE operation may appear to
454 The use of ACQUIRE and RELEASE operations generally precludes the need
888 Firstly, write barriers act as partial orderings on store operations.
1659 memory operations appear to a device by prohibiting both the compiler and the
1693 operations" subsection for information on where to use these.
1777 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
1778 for each construct. These operations all imply certain barriers:
1782 Memory operations issued after the ACQUIRE will be completed after the
1785 Memory operations issued before the ACQUIRE may be completed after
1794 Memory operations issued before the RELEASE will be completed before the
1797 Memory operations issued after the RELEASE may be completed before the
1802 All ACQUIRE operations issued before another ACQUIRE operation will be
1807 All ACQUIRE operations issued before a RELEASE operation will be
1868 that matter, the developer) switched the operations, deadlock
1871 But suppose the CPU reordered the operations. In this case,
1897 The operations will always occur in one of the following orders:
1913 with interrupt disabling operations.
2254 (*) Atomic operations.
2269 operations that affect both CPUs may have to be carefully ordered to prevent
2366 operations are noted specially as some of them imply full memory barriers and
2373 explicit lock operations, described later). These include:
2395 operations and adjusting reference counters towards object destruction, and as
2399 The following operations are potential problems as they do _not_ imply memory
2401 operations:
2436 The following operations are special locking primitives:
2442 These implement ACQUIRE-class and RELEASE-class operations. These should be used in
2443 preference to other operations when implementing locking primitives, because
2492 form of locking), such that the critical operations are all contained within
2523 sections will include synchronous load operations on strictly ordered I/O
2593 ordering with respect to LOCK or UNLOCK operations. If the latter is
2639 The way cached memory operations are perceived across the system is affected to
2678 generate load and store operations which then go into the queue of memory
2741 (*) each cache has a queue of operations that need to be applied to that cache
2871 operations in exactly the order specified, so that if the CPU is, for example,
2882 operations as seen by external observers in the system: