Lines Matching refs:caches

559 machines with split caches, so that, for example, one cache bank processes
2640 a certain extent by the caches that lie between CPUs and memory, and by the
2644 caches goes, the memory system has to include the CPU's caches, and memory
2700 caches are expected to be coherent, there's no guarantee that that coherency
2707 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2749 between them to guarantee that they will appear to reach that CPU's caches in
2763 the local CPU's caches have apparently been updated in the correct order.  But
2773 cacheline holding p may get updated in one of the second CPU's caches whilst
2775 CPU's caches by some other cache event:
2825 Other CPUs may also have split caches, but must coordinate between the various
2835 dirty cache lines may be resident in the caches of various CPUs, and may not
2901      of the CPU buses and caches;
2987 caches with the memory coherence system, thus making it seem like pointer