Lines Matching refs:before

164 into Q before issuing the load of *Q.
345      specified before the barrier will appear to happen before all the STORE
353      memory system as time progresses.  All stores before a write barrier will
366      make sure that the target of the second load is updated before the address
399      LOAD operations specified before the barrier will appear to happen before
416      operations specified before the barrier will appear to happen before all
436      Memory operations that occur before an ACQUIRE operation may appear to
446      memory operations before the RELEASE operation will appear to happen
447      before the RELEASE operation with respect to the other components of the
452      happen before it completes.
484  (*) There is no guarantee that any of the memory accesses specified before a
608 the load from b as having happened before the load from a.  In such a
786 that is, just before or just after the "if" statements.
872 [!] Note that the stores before the write barrier would normally be expected to
902 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
915 	|       |  :    | E=5  |     }        barrier to be committed before
1126 before the read barrier completes anyway:
1197 Placing a read barrier or a data dependency barrier just before the second
1640 of b before loading a[b]), however there is no guarantee in the C specification
1642 a before b (eg. tmp = a[1]; if (b != 1) tmp = a[b]; ). There is also the
1690      *before* the reference counter is decremented.
1716 		/* flush modifications before status update */
1722 		/* force memory to sync before notifying device via MMIO */
1730      before we read the data from the descriptor, and the dma_wmb() allows
1731      us to guarantee the data is written to the descriptor before the device
1733      cache coherent memory writes have completed before attempting a write to
1785      Memory operations issued before the ACQUIRE may be completed after
1794      Memory operations issued before the RELEASE will be completed before the
1797      Memory operations issued after the RELEASE may be completed before the
1802      All ACQUIRE operations issued before another ACQUIRE operation will be
1803      completed before that ACQUIRE operation.
1807      All ACQUIRE operations issued before a RELEASE operation will be
1808      completed before the RELEASE operation.
1823 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
1889 seen by other CPUs before the store to *B:
1907 ensures that the store to *A will always be seen as happening before
2013 something up.  The barrier occurs before the task state is cleared, and so sits
2059 order multiple stores before the wake-up with respect to loads of those stored
2204 What is necessary here is to intervene with an mmiowb() before dropping the
2221 before either of the stores issued on CPU 2.
2225 for the mmiowb(), because the load forces the store to complete before the load
2313 before proceeding.  Since the record is on the waiter's stack, this means that
2316 stack before the up*() function has a chance to read the next pointer.
2350 In this case, the barrier makes a guarantee that all memory accesses before the
2351 barrier will appear to happen before all the memory accesses after the barrier
2353 the memory accesses before the barrier will be complete by the time the barrier
2617 earlier instruction must be sufficiently complete[*] before the later
2756 	smp_wmb();			Make sure change to v is visible before
2789 			<C:read *q>	Reads from v before v updated in cache
2800 queue before processing any further requests:
2881 instruction before moving on to the next one, leading to a definite sequence of
2954 The compiler may also combine, discard or defer elements of the sequence before