Lines Matching refs:Memory
84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
326 Memory barriers are such interventions. They impose a perceived partial
332 branch prediction and various types of caching. Memory barriers are used to
340 Memory barriers come in four basic varieties:
436 Memory operations that occur before an ACQUIRE operation may appear to
451 Memory operations that occur after a RELEASE operation may appear to
468 Memory barriers are only required where there's a possibility of interaction
1782 Memory operations issued after the ACQUIRE will be completed after the
1785 Memory operations issued before the ACQUIRE may be completed after
1794 Memory operations issued before the RELEASE will be completed before the
1797 Memory operations issued after the RELEASE may be completed before the
2648 <--- CPU ---> : <----------- Memory ----------->
2652 | CPU | | Memory | : | CPU | | | | |
2654 | | | Queue | : | | | |--->| Memory |
2662 | CPU | | Memory | : | CPU | | |--->| Device |
2688 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2718 : | Memory |
2854 Memory mapped I/O usually takes place through memory locations that are part of
3002 Memory barriers can be used to implement circular buffering without the need
3022 Chapter 7.1: Memory-Access Ordering
3023 Chapter 7.4: Buffering and Combining Memory Writes
3028 Chapter 7.2: Memory Ordering
3032 Chapter 8: Memory Models
3033 Appendix D: Formal Specification of the Memory Models
3034 Appendix J: Programming with the Memory Models
3037 Chapter 5: Memory Accesses and Cacheability
3038 Chapter 15: Sparc-V9 Memory Models
3041 Chapter 9: Memory Models
3044 Chapter 8: Memory Models
3047 Chapter 9: Memory
3048 Appendix D: Formal Specifications of the Memory Models
3051 Chapter 8: Memory Models
3060 Chapter 13: Other Memory Models
3064 Section 4.4: Memory Access