Lines Matching refs:B
117 { A == 1; B == 2 }
118 A = 3; x = B;
119 B = 4; y = A;
124 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
125 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
126 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
127 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
128 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
129 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
130 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
131 STORE B=4, ...
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
152 B = 4; Q = P;
153 P = &B D = *Q;
160 (Q == &B) and (D == 2)
161 (Q == &B) and (D == 4)
240 X = *A; Y = *B; *D = Z;
244 X = LOAD *A, Y = LOAD *B, STORE *D = Z
245 X = LOAD *A, STORE *D = Z, Y = LOAD *B
246 Y = LOAD *B, X = LOAD *A, STORE *D = Z
247 Y = LOAD *B, STORE *D = Z, X = LOAD *A
248 STORE *D = Z, X = LOAD *A, Y = LOAD *B
249 STORE *D = Z, Y = LOAD *B, X = LOAD *A
520 { A == 1, B == 2, C = 3, P == &A, Q == &C }
521 B = 4;
523 ACCESS_ONCE(P) = &B
528 sequence, Q must be either &A or &B, and that:
531 (Q == &B) implies (D == 4)
533 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
536 (Q == &B) and (D == 2) ????
547 { A == 1, B == 2, C = 3, P == &A, Q == &C }
548 B = 4;
550 ACCESS_ONCE(P) = &B
562 variable B might be stored in an even-numbered cache line. Then, if the
564 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
565 but the old value of the variable B (2).
894 STORE B = 2
902 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
911 | CPU 1 | : | B=2 | }
931 { B = 7; X = 9; Y = 8; C = &Y }
933 STORE B = 2
935 STORE C = &B LOAD X
936 STORE D = 4 LOAD C (gets &B)
937 LOAD *C (reads B)
944 | |------>| B=2 |----- --->| Y->8 | | of perception on
950 | | : | C=&B |--- | : : +-------+
952 | |------>| D=4 | ----------->| C->&B |------>| |
958 Apparently incorrect ---> | | B->7 |------>| |
959 perception of B (!) | +-------+ | |
964 of coherence of B ----->| B->2 | +-------+
969 In the above example, CPU 2 perceives that B is 7, despite the load of *C
970 (which would be B) coming after the LOAD of C.
973 and the load of *C (ie: B) on CPU 2:
977 { B = 7; X = 9; Y = 8; C = &Y }
979 STORE B = 2
981 STORE C = &B LOAD X
982 STORE D = 4 LOAD C (gets &B)
984 LOAD *C (reads B)
990 | |------>| B=2 |----- --->| Y->8 |
996 | | : | C=&B |--- | : : +-------+
998 | |------>| D=4 | ----------->| C->&B |------>| |
1008 are perceptible to ----->| B->2 |------>| |
1018 { A = 0, B = 9 }
1021 STORE B=2
1022 LOAD B
1032 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1034 | |------>| B=2 |--- | : :
1037 ---------->| B->2 |------>| |
1049 If, however, a read barrier were to be placed between the load of B and the
1054 { A = 0, B = 9 }
1057 STORE B=2
1058 LOAD B
1069 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1071 | |------>| B=2 |--- | : :
1074 ---------->| B->2 |------>| |
1080 prior to the storage of B ---->| A->1 |------>| |
1090 { A = 0, B = 9 }
1093 STORE B=2
1094 LOAD B
1099 Even though the two loads of A both occur after the load of B, they may both
1106 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1108 | |------>| B=2 |--- | : :
1111 ---------->| B->2 |------>| |
1120 prior to the storage of B ---->| A->1 |------>| 2nd |
1132 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1134 | |------>| B=2 |--- | : :
1137 ---------->| B->2 |------>| |
1152 load of B came up with B == 2. No such guarantee exists for the first load of
1174 LOAD B
1183 --->| B->2 |------>| |
1202 LOAD B
1214 --->| B->2 |------>| |
1236 --->| B->2 |------>| |
1275 CPU A follows a load from the same variable executing on CPU B, then
1276 CPU A's load must either return the same value that CPU B's load did,
1829 *B = b;
1833 ACQUIRE M, STORE *B, STORE *A, RELEASE M
1854 *B = b;
1858 ACQUIRE N, STORE *B, STORE *A, RELEASE M
1889 seen by other CPUs before the store to *B:
1895 *B = b;
1899 STORE *A, RELEASE, ACQUIRE, smp_mb__after_unlock_lock(), STORE *B
1900 STORE *A, ACQUIRE, RELEASE, smp_mb__after_unlock_lock(), STORE *B
1901 ACQUIRE, STORE *A, RELEASE, smp_mb__after_unlock_lock(), STORE *B
1908 the store to *B.
1921 *B = b;
1931 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
1937 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
1938 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
1939 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
1940 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
2121 ACCESS_ONCE(*B) = b; ACCESS_ONCE(*F) = f;
2130 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2134 *B, *C or *D preceding ACQUIRE M
2135 *A, *B or *C following RELEASE M
2146 ACCESS_ONCE(*B) = b;
2159 *E, ACQUIRE M [1], *C, *B, *A, RELEASE M [1],
2164 *B, *C, *D, *F, *G or *H preceding ACQUIRE M [1]
2165 *A, *B or *C following RELEASE M [1]
2167 *A, *B, *C, *E, *F or *G following RELEASE M [2]
2707 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2716 +--------+ : +--->| Cache B |<------->| |
2734 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2760 <B:modify p=&v> p is now in cache B exclusively
2786 <B:modify p=&v> <D:commit p=&v>
2811 <B:modify p=&v> <D:commit p=&v>
2875 ACCESS_ONCE(*B) = b;
2884 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2916 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B