Lines Matching refs:be

11 registers, thus requiring at least one general purpose register to be
14 This cannot be extended to modules for the displacement is likely to be too
15 far. Thus in modules the address of a function to call must be calculated
54       available that may be accessed in this mode, in addition to all the
60 	  handler. On entry to the handler, the PSR.T bit will be cleared.
71       management exceptions will be flagged for later consideration, but
72       the exception handler won't be invoked. Debugging traps such as
73       hardware breakpoints and watchpoints will be ignored. This mode is
76       All kernel mode registers may be accessed, plus a few extra debugging
142 (including the stack pointer) may be changed.
154 ops, so it must be exceedingly careful not to do any that would interact
184      virtually enabled. Can be modified by logical instructions without
208 	ICC2.Z would be set to 0.
211      be used to trap if interrupts were now virtually enabled, but
213      kernel would then be back to state (1).
222 	ICC2.Z would be shifted into the save variable and masked off 
225 	ICC2.Z would then be set to 1 (thus unchanged), and ICC2.C would be
230 	ICC2.Z would be set to indicate the result of XOR'ing the saved
236      A TIHI #2 instruction would be used to again assay the current state,
241 	ICC2.Z would be cleared. ICC2.C would be left unaffected. Both
242 	flags would now be 0.
246      [interrupts really disabled] would then be true.
251 (10) Immediately upon returning, the pending interrupt would be taken.
257      interrupts are definitely enabled - or else the kernel wouldn't be here.
259 (13) On return from the interrupt handler, things would be back to state (1).