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6 instruction. Unfortunately, this alone can't be used to implement the following operations:
8  (*) Atomic add to memory
16 On such CPUs, the standard way of emulating such operations in uniprocessor mode is to disable
17 interrupts, but on the FR-V CPUs, modifying the PSR takes a lot of clock cycles, and it has to be
26 To get around this, the following algorithm has been implemented. It operates in a way similar to
29  (*) The CCCR.CC3 register is reserved within the kernel to act as an atomic modify abort flag.
31  (*) In the exception prologues run on kernel->kernel entry, CCCR.CC3 is set to 0 (Undefined
36      (1) Set ICC3.Z to true and set CC3 to True (ORCC/CKEQ/ORCR).
38      (2) Load the value currently in the memory to be modified into a register.
40      (3) Make changes to the value.
44 	 (a) Store the modified value back to memory.
46 	 (b) Set ICC3.Z to false (CORCC on GR29 is sufficient for this - GR29 holds the current
47 	     task pointer in the kernel, and so is guaranteed to be non-zero).
49      (5) If ICC3.Z is still true, go back to step (1).
52 steps (1) and (4) will set CC3 to the Undefined, thus aborting the store in (4a), and causing the
53 condition in ICC3 to remain with the Z flag set, thus causing step (5) to loop back to step (1).
59      not any changes were made to the target memory location during that exception.
61  (2) The branch from step (5) back to step (1) may have to happen more than once until the store
62      manages to take place. In theory, this loop could cycle forever because there are too many
78 It starts by setting ICC3.Z to true for later use, and also transforming that into CC3 being in the
96 Then it attempts to store the value back, contingent on no exception having cleared CC3 since it
97 was set to True.
131    - no out-of-line function calls need to be made