Lines Matching refs:memory

40 In the initial release, memory Correctable Errors (CE) and Uncorrectable
47 proactive part replacement of memory DIMMs exhibiting CEs can reduce
55 This new device type allows for non-memory type of ECC hardware detectors
128 loads both the amd76x_edac.ko memory controller module and the edac_mc.ko
142 	mc	memory controller(s) system
149 First a background on the memory controller's model abstracted in EDAC.
150 Each 'mc' device controls a set of DIMM memory modules. These modules are
156 of a given motherboard, memory controller and DIMM characteristics.
158 Dual channels allows for 128 bit data transfers to the CPU from memory.
175 for memory DIMMs:
186 based on the slot into which the memory DIMM is placed. Thus, when 1 DIMM
198 /sys/devices/system/edac/mc each memory controller will be represented
235 this 'X' instance of the memory controllers.
275 Total memory managed by this csrow attribute file:
279 	This attribute file displays, in count of megabytes, of memory
287 	This attribute file will display what type of memory is currently
288 	on this csrow. Normally, either buffered or unbuffered memory.
394 	the memory controller			(MC0)
396 	memory page				(0x283)
401 	memory row				(row 0)
402 	memory channel				(channel 1)
407 Both UEs and CEs with no info will lack all but memory controller,
665    Each QPI is exported as a different memory controller.
670    For injecting a memory error, there are some sysfs nodes, under
677          rank = the memory rank;
736 3) Nehalem specific Corrected Error memory counters
738    Nehalem have some registers to count memory errors. The driver uses those
758    So, in this memory mapping: