Lines Matching refs:a
10 They have a given number of channels to use for the DMA transfers, and
11 a given number of requests lines.
20 will want to start a transfer, it will assert a DMA request (DRQ) by
23 A very simple DMA controller would only take into account a single
24 parameter: the transfer size. At each clock cycle, it would transfer a
29 require a specific number of bits to be transferred in a single
31 physical bus allows to maximize performances when doing a simple
32 memory copy operation, but our audio device could have a narrower FIFO
33 that requires data to be written exactly 16 or 24 bits at a time. This
34 is why most if not all of the DMA controllers can adjust this, using a
37 Moreover, some DMA controllers, whenever the RAM is used as a source
38 or destination, can group the reads or writes in memory into a buffer,
39 so instead of having a lot of small memory accesses, which is not
41 using a parameter called the burst size, that defines how many single
46 that involve a single contiguous block of data. However, some of the
48 non-contiguous buffers to a contiguous buffer, which is called
52 scatter-gather. So we're left with two cases here: either we have a
54 implement it in software, or we have a more advanced DMA controller,
57 The latter are usually programmed using a collection of chunks to
61 This collection is usually either a table or a linked list. You will
64 and whenever a DRQ will be asserted, it will go through the collection
68 your hardware. Each DMA controller will require a different structure,
91 dmaengine was extended. Nowadays, the async TX API is written as a
92 layer on top of dmaengine, and acts as a client. Still, dmaengine
106 relies on the driver filling a structure and registering against the
111 need to initialize a few fields in there:
113 * channels: should be initialized as a list using the
117 - should contain a bitmask of the supported source transfer width
120 - should contain a bitmask of the supported destination transfer
124 - should contain a bitmask of the supported slave directions
132 reporting. The framework will only know that a particular
150 Our dma_device structure has a field called cap_mask that holds the
168 algorithm against a memory buffer.
171 - The device is able to perform RAID6 P+Q computations, P being a
172 simple XOR, and Q being a Reed-Solomon algorithm.
176 algorithm against a memory buffer.
179 - The device is able to trigger a dummy transfer that will
181 - Used by the client drivers to register a callback that will be
182 called on a regular basis through the DMA controller interrupt
187 - Even though a plain memcpy can look like a particular case of a
188 scatter-gather transfer, with a single chunk to transfer, it's a
204 deal with a single chunk to copy or a collection of them, here,
205 we just have a single transaction type that is supposed to
207 - If you want to transfer a single contiguous memory buffer,
208 simply build a scatter list with only one item.
212 - A cyclic transfer is a transfer where the chunk collection will
215 on a single ring buffer that you will fill with your audio data.
219 - These transfers can transfer data from a non-contiguous buffer
220 to a non-contiguous buffer, opposed to DMA_SLAVE that can
221 transfer data from a non-contiguous data set to a continuous
224 want to transfer a portion of uncompressed data directly to the
231 after each transfer. In case of a ring buffer, they may loop
232 (DMA_CYCLIC). Addresses pointing to a device's register (e.g. a FIFO)
238 Our dma_device structure also requires a few function pointers in
248 - These functions will be called whenever a driver will call
260 for the transfer being prepared, and should create a hardware
261 descriptor or a list of hardware descriptors from it
270 - It should return a unique instance of the
281 + tx_submit: A pointer to a function you have to implement,
283 transaction descriptor to a pending queue, waiting
295 argument, not the currently active one on a given channel
298 - In the case of a cyclic transfer, it should only take into
307 - In this case, the function will receive a dma_slave_config
310 - Even though that structure contains a direction field, this
315 If a driver support both, it should use this call for slave
319 - Pauses a transfer on the channel
324 - Resumes a transfer on the channel
343 - it's a DMA transaction ID that will increment over time.
357 Most of the DMAEngine drivers you'll see are based on a similar design
359 most work to a tasklet, including the start of a new transfer whenever
362 This is a rather inefficient design though, because the inter-transfer
367 You should avoid this kind of practice, and instead of electing a new
369 order to have a shorter idle window (that we can't really avoid