Lines Matching refs:msi
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
21 be set as edge sensitive. If msi-available-ranges is present, only
30 - msi-available-ranges: use <start count> style section to define which
31 msi interrupt can be used in the 256 msi interrupts. This property is
38 - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
48 msi@41600 {
49 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
51 msi-available-ranges = <0 0x100>;
64 msi@41600 {
65 compatible = "fsl,mpic-msi-v4.3";
86 The Freescale hypervisor and msi-address-64
114 this. The address specified in the msi-address-64 property is the PCI