Lines Matching refs:of

5 and also provides ability to multiplex and configure the output of various
9 - compatible: should be one of the following.
23 - reg: Base address of the pin controller hardware module and length of
26 - Pin banks as child nodes: Pin banks of the controller are represented by child
27   nodes of the controller node. Bank name is taken from name of the node. Each
31   - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
32     binding is used, the amount of cells must be specified as 2. See the below
33     mentioned gpio binding representation for description of particular cells.
36 	<[phandle of the gpio controller node]
47   as child nodes of the pin-controller node. There should be atleast one
48   child node and there is no limit on the count of these child nodes. It is
49   also possible for a child node to consist of several further child nodes
50   to allow grouping multiple pinctrl groups into one. The format of second
54   The child node should contain a list of pin(s) on which a particular pin
56   list of pins is specified using the property name "samsung,pins". There
58   limit on the count of pins that can be specified. The pins are specified
59   using pin names which are derived from the hardware manual of the SoC. As
60   an example, the pins in GPA0 bank of the pin controller can be represented
62   The format of the pin names should be (as per the hardware manual)
67   of this property that should be applied to each of the pins listed in the
68   "samsung,pins" property should be picked from the hardware manual of the SoC
71   node. The value of this property is used as-is to program the pin-controller
72   function selector register of the pin-bank.
74   The child node can also optionally specify one or more of the pin
76   "samsung,pins" property of the child node. The following pin configuration
79   - samsung,pin-val: Initial value of pin output buffer.
87   pull up/down and driver strength register of the pin-controller.
98 The controller supports two types of external interrupts over gpio. The first
106    - interrupt-parent: phandle of the interrupt parent to which the external
108    - interrupts: interrupt specifier for the controller. The format and value of
111    In addition, following properties must be present in node of every bank
112    of pins supporting GPIO interrupts:
115    - #interrupt-cells: the value of this property should be 2.
117        external gpio interrupt space of the controller.
118      - Second Cell: flags to identify the type of the interrupt
130    - compatible: identifies the type of the external wakeup interrupt controller
142    - interrupt-parent: phandle of the interrupt parent to which the external
146    In addition, following properties must be present in node of every bank
147    of pins supporting wake-up interrupts:
150    - #interrupt-cells: the value of this property should be 2
152        the external wakeup interrupt space of the controller.
153      - Second Cell: flags to identify the type of the interrupt
160    Node of every bank of pins supporting direct wake-up interrupts (without
163    - interrupt-parent: phandle of the interrupt parent to which the external
165    - interrupts: interrupts of the interrupt parent which are used for external
166      wakeup interrupts from pins of the bank, must contain interrupts for all
167      pins of the bank.
175 - pinctrl0: pin controller of ALIVE block,
176 - pinctrl1: pin controller of BUS0 block,
177 - pinctrl2: pin controller of NFC block,
178 - pinctrl3: pin controller of TOUCH block,
179 - pinctrl4: pin controller of FF block,
180 - pinctrl5: pin controller of ESE block,
181 - pinctrl6: pin controller of FSYS0 block,
182 - pinctrl7: pin controller of FSYS1 block,
183 - pinctrl8: pin controller of BUS1 block,
184 - pinctrl9: pin controller of AUDIO block,