Lines Matching refs:mailbox

4 The OMAP mailbox hardware facilitates communication between different processors
5 using a queued mailbox interrupt mechanism. The IP block is external to the
10 Each mailbox IP block has a certain number of h/w fifo queues and output
36 			    "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
37 			    "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
38 			    "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
40 - reg:			Contains the mailbox register address range (base
42 - interrupts:		Contains the interrupt information for the mailbox
45 - ti,hwmods:		Name of the hwmod associated with the mailbox
46 - #mbox-cells:		Common mailbox binding property to identify the number
47 			of cells required for the mailbox specifier. Should be
49 - ti,mbox-num-users:	Number of targets (processor devices) that the mailbox
51 - ti,mbox-num-fifos:	Number of h/w fifo queues within the mailbox IP block
55 A child node is used for representing the actual sub-mailbox device that is
58 mailbox device nodes.
62 - ti,mbox-tx:		sub-mailbox descriptor property defining a Tx fifo
63 - ti,mbox-rx:		sub-mailbox descriptor property defining a Rx fifo
65 Sub-mailbox Descriptor Data
69     Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
75     Cell #3 (usr_id)  - mailbox user id for identifying the interrupt line
81 them using the common mailbox binding properties, "mboxes" and the optional
82 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
84 mailbox controller device node and an args specifier that will be the phandle to
85 the intended sub-mailbox child node to be used for communication. The equivalent
94 mailbox: mailbox@4a0f4000 {
95 	compatible = "ti,omap4-mailbox";
98 	ti,hwmods = "mailbox";
114 	mboxes = <&mailbox &mbox_dsp>;
119 mailbox: mailbox@480C8000 {
120 	compatible = "ti,omap4-mailbox";
123 	ti,hwmods = "mailbox";