Lines Matching refs:interrupt

5 using a queued mailbox interrupt mechanism. The IP block is external to the
8 interrupt configuration registers.
11 interrupt lines. An output interrupt line is routed to an interrupt controller
13 specific processor's interrupt controller. The interrupt line connections are
15 (excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
16 programmable through a set of interrupt configuration registers, and have a rx
17 and tx interrupt source per h/w fifo. Communication between different processors
18 is achieved through the appropriate programming of the rx and tx interrupt
19 sources on the appropriate interrupt lines.
21 The number of h/w fifo queues and interrupt lines dictate the usable registers.
24 and interrupt lines between different instances. The interrupt lines can also be
26 the Crossbar, a kind of interrupt router/multiplexer.
42 - interrupts:		Contains the interrupt information for the mailbox
43 			device. The format is dependent on which interrupt
50 			device can interrupt
74                         multiple interrupt lines connected to the MPU processor.
75     Cell #3 (usr_id)  - mailbox user id for identifying the interrupt line
76                         associated with generating a tx/rx fifo interrupt.