Lines Matching refs:MMU

1 Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
7 System MMU is an IOMMU and supports identical translation table format to
9 permissions, shareability and security protection. In addition, System MMU has
15 master), but one System MMU can handle transactions from only one peripheral
16 device. The relation between a System MMU and the peripheral device needs to be
21 * MFC has one System MMU on its left and right bus.
22 * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
24 * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
25   the other System MMU on the write channel.
28 System MMU.
31 The current DT binding for the Exynos System MMU is incomplete.
37 - reg: A tuple of base address and size of System MMU registers.
38 - interrupt-parent: The phandle of the interrupt controller of System MMU
39 - interrupts: An interrupt specifier for interrupt signal of System MMU,
42 - clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
43 	       Optional "master" if the clock to the System MMU is gated by
47 - clocks: Required if the System MMU is needed to gate its clock.
48 - power-domains: Required if the System MMU is needed to gate its power.