Lines Matching refs:of
3 ARM SoCs may contain an implementation of the ARM System Memory
5 of address translation to bus masters external to the CPU.
12 - compatible : Should be one of:
21 version of the architecture implemented.
23 - reg : Base address and size of the SMMU.
25 - #global-interrupts : The number of global interrupts exposed by the
31 specified in order of their indexing by the SMMU.
34 interrupt per context bank. In the case of a single,
37 - mmu-masters : A list of phandles to device nodes representing bus
41 "#stream-id-cells" property, indicating the number of
46 - calxeda,smmu-secure-config-access : Enable proper handling of buggy
49 aliases of secure registers have to be used during