Lines Matching refs:of

23 SEC 4 h/w can process requests from 2 types of sources.
30 such as the P4080.  The number of simultaneous dequeues the QI can make is
31 equal to the number of Descriptor Controller (DECO) engines in a particular
46     Node defines the base address of the SEC 4 block.
47     This block specifies the address range of all global
62       Definition: A standard property. Define the 'ERA' of the SEC
68        Definition: A standard property.  Defines the number of cells
74        Definition: A standard property.  Defines the number of cells
75            for representing the size of physical addresses in
82           address and length of the SEC4 configuration registers.
89            range of the SEC 4.0 register space (-SNVS not included).  A
97            device.  The value of the interrupts property
98            consists of one interrupt specifier. The format
99            of the specifier is defined by the binding document
128     Child of the crypto node defines data processing interface to SEC 4
129     across the peripheral bus for purposes of processing
133     the address range of this node.
160            device.  The value of the interrupts property
161            consists of one interrupt specifier. The format
162            of the specifier is defined by the binding document
185   Child node of the crypto node.  Defines a register space that
186   contains up to 5 sets of addresses and their lengths (sizes) that
201        Definition: A standard property.  Defines the number of cells
203            have a value of 1.
208        Definition: A standard property.  Defines the number of cells
209            for representing the size of physical addresses in
210            child nodes.  Must have a value of 1.
223            range of the SEC 4 register space (-SNVS not included).  A
239   perform run-time integrity check of memory areas that should not modified.
255           1. The location of the RTIC memory address & length registers.
263            followed by the length of the HW partition to be checked;
302           address and length of the SEC4 configuration
308        Definition: A standard property.  Defines the number of cells
310            have a value of 1.
315        Definition: A standard property.  Defines the number of cells
316            for representing the size of physical addresses in
317            child nodes.  Must have a value of 1.
323            range of the SNVS register space.  A triplet that includes
330            device.  The value of the interrupts property
331            consists of one interrupt specifier. The format
332            of the specifier is defined by the binding document
365           address and length of the SNVS LP configuration registers.