Lines Matching refs:of

9 3 output clocks are accessible. The internal structure of the clock
15 - compatible: shall be one of "silabs,si5351{a,a-msop,b,c}".
18 - clocks: from common clock binding; list of parent clock
26 - silabs,pll-source: pair of (number, source) for each pll. Allows
27   to overwrite clock source of pll A (number=0) or B (number=1).
31 Each of the clock outputs can be overwritten individually by
36 - reg: number of clock output.
39 - silabs,clock-source: source clock of the output divider stage N, shall be
44 - silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
45 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
77 		/* connect xtal input as source of pll0 and pll1 */
83 		 * - pll0 as clock source of multisynth0
84 		 * - multisynth0 as clock source of output divider
86 		 * - set initial clock frequency of 74.25MHz
100 		 * - pll1 as clock source of multisynth1
101 		 * - multisynth1 as clock source of output divider
114 		 * - xtal as clock source of output divider