Lines Matching refs:Clock

1 * Gated Clock bindings for Marvell EBU SoCs
11 ID	Clock	Peripheral
14 1	pex0_en	PCIe 0 Clock out
15 2	pex1_en	PCIe 1 Clock out
27 ID	Clock		Peripheral
32 5	pex0		PCIe 0 Clock out
33 6	pex1		PCIe 1 Clock out
54 ID	Clock		Peripheral
81 ID	Clock		Peripheral
93 ID	Clock	Peripheral
120 ID	Clock	Peripheral
143 ID	Clock	Peripheral
171 - reg : shall be the register address of the Clock Gating Control register