Lines Matching refs:core

6   The core interrupt controller provides 16 prioritized interrupts to the
7   C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
9   sources coming from outside the core.
13   - compatible: Should be "ti,c64x+core-pic";
18   Single cell specifying the core interrupt priority level (4-15) where
26 	compatible = "ti,c64x+core-pic";
35   may be cascaded into the core interrupt controller. The megamodule PIC
36   has a total of 12 outputs cascading into the core interrupt controller.
37   One for each core interrupt priority level. In addition to the combined
39   the core interrupt controller. When an individual interrupt is cascaded,
41   considered to have the core interrupt controller as the parent.
49   - interrupt-parent: must be core interrupt controller
51                 The cells contain the core priority interrupt to which the
56   - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
58                              core priority 4 and the last cell corresponds to
59                              core priority 15. The value of each cell is the
61                              the core interrupt corresponding to the cell
69   interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
70   use the core interrupt controller as their parent and the specifier will
71   be the core priority level, not the megamodule interrupt number.
85   combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
102   mapped directly to core priority interrupt 8. The node using this interrupt
103   must set the core controller as its interrupt parent and use 8 in the