Lines Matching refs:power

26 Retention: Retention is a low power state where the core is clock gated and
33 Standalone PC: A cpu can power down and warmboot if there is a sufficient time
35 to indicate a core entering a power down state without consulting any other
36 cpu or the system resources. This helps save power only on that core.  The SPM
37 sequence for this idle state is programmed to power down the supply to the
38 core, wait for the interrupt, restore power to the core, and ensure the
40 resume. Applying power and resetting the core causes the core to warmboot
42 kernel. Entering a power down state for the cpu, needs to be done by trapping
49 modes. In a hierarchical power domain SoC, this means L2 and other caches can
52 power modes possible at this state is vast, the exit latency and the residency
53 of this low power mode would be considered high even though at a cpu level,
54 this essentially is cpu power down. The SPM in this state also may handshake
55 with the Resource power manager (RPM) processor in the SoC to indicate a