Lines Matching refs:interrupt

8 Secondary GICs are cascaded into the upward interrupt controller and do not
23 - interrupt-controller : Identifies the node as an interrupt controller
24 - #interrupt-cells : Specifies the number of cells needed to encode an
25   interrupt source.  The type shall be a <u32> and the value shall be 3.
27   The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
30   The 2nd cell contains the interrupt number for the interrupt type.
40 	bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
42 	the interrupt is wired to that CPU.  Only valid for PPI interrupts.
53 - interrupts	: Interrupt source of the parent interrupt controller on
54   secondary GICs, or VGIC maintenance interrupt on primary GIC (see
63 	intc: interrupt-controller@fff11000 {
65 		#interrupt-cells = <3>;
67 		interrupt-controller;
77 primary interrupt controller).
86 - interrupts : VGIC maintenance interrupt.
90 	interrupt-controller@2c001000 {
92 		#interrupt-cells = <3>;
93 		interrupt-controller;
127 	interrupt-controller@e1101000 {
129 		#interrupt-cells = <3>;
132 		interrupt-controller;