Lines Matching refs:bits

23   the reg property contained in bits 7 down to 0
58 			  MPIDR_EL1[63:32] bits are not used for CPUs
83 			  required and matches the CPUID[11:0] register bits.
86 			  bits [11:0] in CPU ID register.
88 			  All other bits in the reg cell must be set to 0.
92 			  bits.
95 			  bits [23:0] in MPIDR.
97 			  All other bits in the reg cell must be set to 0.
100 			  and matches the MPIDR_EL1 register affinity bits.
104 			    The first reg cell bits [7:0] must be set to
105 			    bits [39:32] of MPIDR_EL1.
107 			    The second reg cell bits [23:0] must be set to
108 			    bits [23:0] of MPIDR_EL1.
112 			    The reg cell bits [23:0] must be set to bits [23:0]
115 			  All other bits in the reg cells must be set to 0.