Lines Matching refs:timer

1 * ARM architected timer
3 ARM cores may have a per-core architected timer, which provides per-cpu timers,
4 or a memory mapped architected timer, which provides up to 8 frames with a
5 physical and optional virtual timer per frame.
7 The per-core architected timer is attached to a GIC to deliver its
8 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
14 	"arm,armv7-timer"
15 	"arm,armv8-timer"
25 - always-on : a boolean property. If present, the timer is powered through an
31   any of the generic timer CPU registers, which contain their
38 	timer {
39 		compatible = "arm,cortex-a15-timer",
40 			     "arm,armv7-timer";
48 ** Memory mapped timer node properties:
50 - compatible : Should at least contain "arm,armv7-timer-mem".
60 A timer node has up to 8 frame sub-nodes, each with the following properties:
65   The virtual timer interrupt is optional.
74 	timer@f0000000 {
75 		compatible = "arm,armv7-timer-mem";