Lines Matching refs:must

48 The device tree blob (dtb) must be placed on an 8-byte boundary within
49 the first 512 megabytes from the start of the kernel image and must not
99   little-endian and must be respected.  Where image_size is zero,
112 The Image must be placed text_offset bytes from a 2MB aligned base
116 At least image_size bytes from the start of the image must be free for
124 Before jumping into the kernel, the following conditions must be met:
137   All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
139   The CPU must be in either EL2 (RECOMMENDED in order to have access to
143   The MMU must be off.
145   The address range corresponding to the loaded kernel image must be
150   operations must be configured and may be enabled.
152   operations (not recommended) must be configured and disabled.
155   CNTFRQ must be programmed with the timer frequency and CNTVOFF must
157   kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
161   All CPUs to be booted by the kernel must be part of the same coherency
168   the kernel image will be entered must be initialised by software at a
173     ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
174     ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
176     ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
177     ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
180 timers, coherency and system registers apply to all CPUs.  All CPUs must
186 - The primary CPU must jump directly to the first instruction of the
187   kernel image.  The device tree blob passed by this CPU must contain
194 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
200   device tree) polling their cpu-release-addr location, which must be
204   cpu-release-addr returns a non-zero value, the CPU must jump to this
206   value, so CPUs must convert the read value to their native endianness