Lines Matching refs:and

8  the ability to change the core, memory and peripheral operating
13  There are two forms of the driver depending on the specific CPU and
15  PLL to feed the ARM, memory and peripherals via a series of dividers
16  and muxes and this is the implementation that is documented here. A
17  newer version where there is a separate PLL and clock divider for the
25  need to register and the interface to the generic drivers/cpufreq
27  and anything else associated with it. Any board that wants to use this
38  SoC and the driver as each device has different PLL and clock chains
45  The SLOW mode where the PLL is turned off altogether and the
62  board requires and any restrictions being placed on it.
65  timings changing, any maximum frequency limits and information about the